Difference between revisions of "CODA Summary"

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== S1 ==
 
== S1 ==
  
initSIS in SIS3801[0] at addr 90a40000  
+
  initSIS in SIS3801[0] at addr 90a40000  
initSIS in SIS3801[0] at addr 90a50000
+
  initSIS in SIS3801[0] at addr 90a50000
  
 
== S2 ==
 
== S2 ==

Revision as of 09:21, 30 October 2013

Summary of CODA Configurations

Name Readout Output Trigger
Scalers Scaler S1 (helicity gated), S2 (un-gated) Scalers_%d.dat Delayed nT_Settle
Mott_Sample Mott FADC, S1, S2, TDC Mott_Sample_%d.dat Mott Detector
Mott_SemiInt Mott FADC, S1, S2, TDC Mott_SemiInt_%d.dat Mott Detector
FADC_Int INT FADC, S1, S2 FADC_Int_%d.dat nT_Settle


Mott FADC

 const FADC_ADDR       = 0x680000  # 12 bit fADC MOTT - Slot 7
 const FADCMODE        = 1 (Mott_Sample)
 const FADCMODE        = 3 (Mott_SemiInt)
 const FADCSLOT_Mott   = 7
 const TRSPLIT         = 0xeb13   # Address of fADC Signal Distribution Module


INT FADC

 const FADC_ADDR       = 0xed0000  # 12 bit fADC Int - Slot 10         
 const FADCMODE        = 3 (Int_Int, special)
 const FADCSLOT_PEPPo3 = 10
 const TRSPLIT         = 0xea13   # Address of fADC Signal Distribution Module


TDC

 CAEN v775
 const int V775_ADD    = 0x1190


S1

 initSIS in SIS3801[0] at addr 90a40000 
 initSIS in SIS3801[0] at addr 90a50000

S2

TID

 A24 Address for TID Module (0x100000 for VME Slot 2)
 const TRIG_ADDR       = 0x100000