Difference between revisions of "OVERVIEW OF SPECIFICATIONS"
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| − | NUMBERS FROM 2021 DETECTOR PROPOSAL DEVELOPMENT - SUPERSEDED | + | === NUMBERS FROM 2021 DETECTOR PROPOSAL DEVELOPMENT - SUPERSEDED === |
'''Coverage: -4 < eta < ~-1''' | '''Coverage: -4 < eta < ~-1''' | ||
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| − | '''Readout Example JLab:''' | + | == '''Readout Example JLab:'''== |
:* fADC-250 MHz 12 bit, 16 channels/VME slot; | :* fADC-250 MHz 12 bit, 16 channels/VME slot; | ||
:* 3us buffer; | :* 3us buffer; | ||
:* FPGA processing of waveform: zero suppression, pulse integral, max amplitude timing (<1 ns) -> readout; | :* FPGA processing of waveform: zero suppression, pulse integral, max amplitude timing (<1 ns) -> readout; | ||
:* VXS: for L1 trigger or for Streaming Readout | :* VXS: for L1 trigger or for Streaming Readout | ||
Revision as of 14:45, 27 October 2023
EEEMCal Design Requirements
PRESENT DESIGN PARAMETERS (2023)
Coverage: -4 < eta < ~-1
- Rin=9cm, Rout=63cm (-X < eta < -XX)
- Length: 60cm
- Offset from center: -175cm
- Physical Start: -235cm
- Physical End: -175cm
- Weight: ~5000kg
Egamma: 20 MeV – 20 GeV
Energy resolution: 1%+2.5%/sqrtE + 1%/E
Spatial resolution: 1+3%/sqrtE
Time resolution:
Typical signal size: <1V
Sampling rate: 250 MHz
Peaking time: ~4ns
Digitization gate: ~(100-200) ns
Signal rate: =<1 MHz/channel
Signal dynamics
- 2V dynamic range
- ADC 12 bits (0.4095)
- ~5 MeV/count
- ADC threshold: ~15 MeV (3 counts)
Maximum annual dose: ~ 3krad/year (30 Gy/year) EM; 1010 n/cm2 hadronic at top luminosity
Photo Detector: 6x6mm2 SiPM (Hamamatsu S14160; 10um cell)
Number of channels:
Data sparsification/feature extraction:
- Peak (amplitude)
- Integral
- Time
- Pedestal
- Number of samples
- Pulse quality
- Pileup detection and recovery
NUMBERS FROM 2021 DETECTOR PROPOSAL DEVELOPMENT - SUPERSEDED
Coverage: -4 < eta < ~-1
- Inner: Rin=15cm, Rout=49cm (-3.75 < eta < -2.5)
- Outer: Rin=49cm, Rout=133cm (-2.5 < eta < ~-1.5)
Egamma:
- Inner: 20 MeV – 20 GeV
- Outer: 50 MeV – 20 GeV
Energy resolution:
- Inner: 1%+2.5%/sqrtE + 1%/E
- Outer: 2%+4%/sqrtE + 2%/E
Spatial resolution: 1+3%/sqrtE
Time resolution:
Typical signal size: <1V
Sampling rate: 250 MHz
Peaking time: ~4ns
Digitization gate: ~(100-200) ns
Signal rate: =<1 MHz/channel
Signal dynamics
- 2V dynamic range
- ADC 12 bits (0.4095)
- ~5 MeV/count
- ADC threshold: ~15 MeV (3 counts)
Maximum annual dose: ~ 3krad/year (30 Gy/year) EM; 1010 n/cm2 hadronic at top luminosity
Photo Detector: 6x6mm2 SiPM (13360; 25um cell)
Number of channels:
Data sparsification/feature extraction:
- Peak (amplitude)
- Integral
- Time
- Pedestal
- Number of samples
- Pulse quality
- Pileup detection and recovery
Readout Example JLab:
- fADC-250 MHz 12 bit, 16 channels/VME slot;
- 3us buffer;
- FPGA processing of waveform: zero suppression, pulse integral, max amplitude timing (<1 ns) -> readout;
- VXS: for L1 trigger or for Streaming Readout