NPS VTP Serial Connection

uBoot boot interruption for configuration

• When the VME-VXS crate is power cycled, the display will show the uboot process.

Xilinx First Stage Boot Loader 
Release 2015.4	Jan 30 2017-11:51:58
Reset reason register 0x00000040
   [SWDT_RST]  = 0, System Watchdog timer
   [AWDT0_RST] = 0, CPU 0 Watch Timer
   [AWDT1_RST] = 0, CPU 1 Watch Timer
   [SLC_RST]   = 0, Write to soft reset bit
   [DBG_RST]   = 0, Debug command DAP controller
   [SRST_B]    = 0, PS_SRST_B reset signal
   [POR]       = 1, PS_POR_B reset signal
   reserved    = 0, reserved
Devcfg driver initialized 
Silicon Version 3.1
Boot mode is SD
SD: rc= 0
SD Init Done 
Flash Base Address: 0xE0100000
Reboot status register: 0x60400000
Multiboot Register: 0x0000C000
Image Start Address: 0x00000000
Partition Header Offset:0x00000C80
Partition Count: 2
Partition Number: 1
Header Dump
Image Word Len: 0x00015D85
Data Word Len: 0x00015D85
Partition Word Len:0x00015D85
Load Addr: 0x04000000
Exec Addr: 0x04000000
Partition Start: 0x000065D0
Partition Attr: 0x00000010
Partition Checksum Offset: 0x00000000
Section Count: 0x00000001
Checksum: 0xF7FB7F3F
Application
Handoff Address: 0x04000000
In FsblHookBeforeHandoff function 
SUCCESSFUL_HANDOFF
FSBL Status = 0x1


U-Boot 2016.01-00002-g46fc0b8-dirty (Oct 26 2016 - 14:24:01 -0400)

Model: Zynq Jlab VTP Board
Board: Xilinx Zynq
DRAM:  ECC disabled 1 GiB
MMC:   sdhci@e0100000: 0
reading env.bin
In:    serial@e0000000
Out:   serial@e0000000
Err:   serial@e0000000
Model: Zynq Jlab VTP Board
Board: Xilinx Zynq
Net:   ZYNQ GEM: e000b000, phyaddr 0, interface rgmii-id
eth0: ethernet@e000b000

• Boot script can be interrupted during the count down period noted by

Hit any key to stop autoboot: