General EEEMCal Meeting Summary 9/22/23

PARTICIPANTS: Carlos, Hamlet, Jim, Justin, Richard, Ioana, Tanja, Joerg, Renee, Sasha, Silvia Skyorova, Crytur USA

MECAHNICAL DESIGN

COOLING QUESTIONS FROM PROJECT ENGINEERING MEETING

• Air cooling or liquid cooling

• Crystals annealing in situ

• Integration: how to get cooling to the crystals

DISCUSSION

• Similar questions and discussions came up during a recent EPIC TIC meeting

• Electronics go into cooling boxes - cooling with fans

• Cool crystals with cooling plates

• Have provided estimates about cooling needs and lines/volume in spreadsheet (https://brookhavenlab.sharepoint.com/:x:/s/EICPublicSharingDocs/EdH38QZE9HpJrl039jn2-q4BbPvrMv7dTFiLV8--atclKw?e=aVNHPg)

• Action items:

• find out if spreadsheet info is sufficient
• if more information is needed set up a subgroup

READOUT DESIGN

DISCRETE

• Slides from Gerard Visser on FEB concept: https://indico.bnl.gov/event/20529/contributions/80621/attachments/49736/85105/waveform_FEB_for_bwd_ECAL_20230913.pdf

• could also consider design like STAR FCS, with "analog-only" FEB inside: preamp/shaper and SiPM bias circuits only, inside, and digitizers outside (analog signals out to "digitizer" FEB's (what would really be called FEB according to the ePIC electronics naming conventions))
• integrated FEB will be cheaper to develop and considerably cheaper to deploy - long analog cables are expensive - but the alternative is worth thinking about.
• Either way, the RDO would be in platform racks. These "analog-only" FEB would have to mount in same way as proposed full FEB's, and probably should be water-cooled to minimize possible thermal impact, but their power dissipation would be more like 30 mW/ch rather than 120 mW/ch. Long analog signal cables are not cheap though and this will be a contributing factor in decision
• details about the SiPM carrier boards used so far in your tests, or sketched out for final design so far? Any thoughts on the cables & connectors to use for this? How might the SiPM boards be mounted (just glued to crystals individually?)? What are the mechanical constraints / issues in regards to your SiPM boards?

• For the SiPM boards for bench tests in Orsay/Palaiseau, they are very simple: input/output one line though an SMA connector to read the SiPM and then connect them to another test board where the ASIC sits on.
• For the SiPM arrays used in the beam tests: https://userweb.jlab.org/~yeran/SciGlass/5x5_prototype/EIC_SiPM_Array_S141606050HS.pdf and the INFN design
• For the final detector, we were thinking of either gluing the SiPM to the crystals or just hold them is place with some grid pressing on the PCB boards (and adding some optical grease for better contact).

• Timeline (tentative)

• Testbench measurements in January
• Beamtests with prototype boards during the summer 2024 for side-by-side comparison with HCROC

• Action items:

• collect components of the readout chain and start testing on test bench, e.g., with LED
• stay in touch with Gerard

READOUT PHOTOSENSOR

• Presentation by Olivier link to slides on performance calculations for different SiPM models (Hamamatsu vs. Broadcom)

• compare calculations to data
• Broadcom devices look promising

• Prototype linearity low energy measurements (up to ~500 MeV)

• good linearity

• Action items:

• prototype tests to show energy dependence of linearity and energy resolution of Broadcom devices with data - possibly with a scintillator comparable to PWO but with higher light output (YAG?)

RECENT REVIEWS

• Crystal FDR
• SiPM FDR

NEXT MEETING: 6 OCTOBER AT 8AM ET (SIMULATIONS MEETING 29 SEPT AT 9AM ET)