Difference between revisions of "SRO RTDP Nov. 18, 2024"

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=== Minutes ===
 
=== Minutes ===
 +
 +
Attendees: David L., Mike G., Jeng T.
 +
 +
* Vardan and Cissie were away at SC24 this week
 +
 +
* We briefly discussed the CLAS12 packet capture data
 +
** Processing of that data is still stalled. We need to gain heavy momentum there so we can demonstrate a physics signal from the data. (e.g. pi0 peak)
 +
** David will discuss with Nathan how to move this forward
 +
 +
* Discussion of milestones M16-M18 that create proxy components for an effects-based simulation
 +
** Mike will start working on a stand-alone CPU component.
 +
*** This will require an initial list of configuration parameters (e.g. Nthreads, latency, etc...)
 +
*** Data ingress/egress may be controlled via reading/writing a socket
 +
*** Work on GPU and FPGA components will follow once a working CPU component is established
 +
 +
* Jeng reported on work to get a cycl workflow running on slurm with 3 processes (iperf3 server+client and prometheus DB server)
 +
** A cycl configuration and a fireworks configuration file were shown. We discussed again how the system would work with DPOL as a master configuration and translators to generate either cycle or fireworks configurations from it
 +
** David expressed concerns that progress on the framework itself and component development has not commenced due to focus on the configurations.
 +
*** Jeng will focus on milestone M15 "Establish general framework for RTDP simulation" that will be capable of utilizing Mike's CPU component
 +
*** A simple configuration format that allows a complete cycle configuration as an element will be implemented allowing RTDP configurations without needing to write a translator
 +
** Cissie will focus on the monitoring infrastructure
  
 
=== Action Items ===
 
=== Action Items ===
 +
 +
* Work on finalizing [https://github.com/JeffersonLab/SRO-RTDP/issues/48 github issue 48] ASAP (Nathan)
 +
* Start development of CPU component to satisfy M16 (Mike)
 +
* Implement basic configuration that embeds cylc configuration (Jeng)
 +
* Finalize monitoring configuration in ifarm (Cissie)

Latest revision as of 16:08, 18 November 2024

The current weekly meeting time is every other Monday at 10:00 US/Eastern

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Agenda:

  1. Previous Meeting
  2. Announcements:
  3. Project Progress: (Github Project)
    1. May 2024 Packet Capture Analysis
    2. RTDP workflow monitoring
    3. RTDP Configuration
  4. BDX Status + R&D
  5. AOT

Milestones


Minutes

Attendees: David L., Mike G., Jeng T.

  • Vardan and Cissie were away at SC24 this week
  • We briefly discussed the CLAS12 packet capture data
    • Processing of that data is still stalled. We need to gain heavy momentum there so we can demonstrate a physics signal from the data. (e.g. pi0 peak)
    • David will discuss with Nathan how to move this forward
  • Discussion of milestones M16-M18 that create proxy components for an effects-based simulation
    • Mike will start working on a stand-alone CPU component.
      • This will require an initial list of configuration parameters (e.g. Nthreads, latency, etc...)
      • Data ingress/egress may be controlled via reading/writing a socket
      • Work on GPU and FPGA components will follow once a working CPU component is established
  • Jeng reported on work to get a cycl workflow running on slurm with 3 processes (iperf3 server+client and prometheus DB server)
    • A cycl configuration and a fireworks configuration file were shown. We discussed again how the system would work with DPOL as a master configuration and translators to generate either cycle or fireworks configurations from it
    • David expressed concerns that progress on the framework itself and component development has not commenced due to focus on the configurations.
      • Jeng will focus on milestone M15 "Establish general framework for RTDP simulation" that will be capable of utilizing Mike's CPU component
      • A simple configuration format that allows a complete cycle configuration as an element will be implemented allowing RTDP configurations without needing to write a translator
    • Cissie will focus on the monitoring infrastructure

Action Items

  • Work on finalizing github issue 48 ASAP (Nathan)
  • Start development of CPU component to satisfy M16 (Mike)
  • Implement basic configuration that embeds cylc configuration (Jeng)
  • Finalize monitoring configuration in ifarm (Cissie)
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