Difference between revisions of "EPSCI Group Meeting May 3, 2021"

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=== Minutes: ===
 
=== Minutes: ===
  
−
<!-- Attendees: David L., Nathan B., Kishan R., Vardan G., Thomas B., Mike G., Torri J., Graham H. -->
+
 
 +
Attendees: Nathan B., Kishan R., Vardan G., Thomas B., Mike G., Torri J., Carl T.
 +
 
 +
* Announcements
 +
** Fortnight paper: There was a suggestion that EPSCI group every focus group (AI, SRO, FPGA based data transfer, etc.) will come up with a paper that would benefit their research.
 +
** Summer internship program: 5 high school students will be working with our group during the June-July time frame.
 +
* Workshop and conferences
 +
** 3 accepted papers at VCHEP2021
 +
** TriDAS group will provide a presenter for the talk on TriDAS+JANA2 paper.
 +
* CI + SPACK
 +
** Summer intern (Jillian) will work on the JLAB common environment.
 +
* EIC
 +
** Graham informed on a new working group formation at the EIC, including David Lawrence, Christiano, and Dmitry Romanov.
 +
** Thomas reported that EIC will be able to submit jobs on OSG through newly created EIC sub VO on the JLAB OSG dedicated resources.
 +
** Brayan is going to increase fair share for the EIC VO, effectively treating EIC as a the 5th experimental Hall.
 +
* JANA2
 +
** Nathan continues working on JANA2 GlueX port, and reported a sizable progress achieved last week.
 +
* CLARA
 +
** v5.0.1 release is not officially deployed as a production version in CLAS12, so nothing to report.
 +
* EJFAT
 +
** ESnet whitebox design is available for review. The design includes an option for a switch based load balancing.
 +
** ESnet suggest using hardware switches equipped with the LAB protocol, where multiple links between two switches combine to provide higher bandwidth links between them.
 +
** PR is being prepared for the FPGA.
 +
** FPGA from the ESnet will be available for tests mid July.
 +
 
 +
* Funding opportunities
 +
** Graham is leading multiple efforts to establish collaborations and projects with real funding opportunities, including an official collaboration with ESnet, ASCR funded  3 phase Data Reduction Pipeline project, and collaboration with BNL on AI model based workflows.
 +
 +
* SRO
 +
** Ed sent Vardan detailed instructions how to operate the SAMPA setup.
 +
** Vardan was able to start the readout and record data from 5 front-end cards in 10 separate files (2 stream per card)..
 +
** Carl and Vardan are continuing to work on VTP and SAMPA setups in the indra-lab.
 +
* CODA
 +
** Carl is finalizing the EVIO-6 release
 +
** Vardan is working on JCEdit to implement FPGA based ROC, a new CODA component type.
 +
* AI
 +
** AI Experimental Controls
 +
*** Torri is leading discussions at the AI WG weekly meetings related to defining critical design requirements and conditions for the project.
 +
** AICEG
 +
*** Kishan  continues to work with Nabuo on the AICEG project. He is evaluating Nabuo’s proposal to use a Lambda layer in the model that will help to incorporate user defined augmented features.
 +
** Hydra
 +
*** Kishan he is trying to use layer-wise relevance propagation method to identify important sections of the histogram image.
 +
*** Two summer interns will work on Hydra project this summer.
 +
* OSG
 +
** Thomas reported that the new feature to bundle similar jobs in the mc-wrapper is chocking CONDOR when the number of bundled jobs in the queue is higher than certain amount (>2000 or so). An obvious solution to this problem, according to Thomas,  would be to introduce a limit on the number of jobs in the queue.
 +
** Two summer students/interns will work on mc-wrapper this summer.

Revision as of 20:13, 3 May 2021

The meeting time is 10:00am.

Connection Info:

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Meeting ID
253 300 597

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Agenda:

  1. Previous meeting
  2. Announcements
  3. Conferences and Workshops
  4. Ongoing Activities
    • EJFAT (ESnet/JLab + FPGA +Accelerated Transport)
      • Status of proposal
    • DAQ systems
      • SRO
        • SAMPA + ERSAP + JANA2 + INDRA-ASTRA = ?
      • CODA (CODA3 support, EVIO-6)
    • A.I.
      • Experimental Controls
      • AIMCEG
      • Multiple FOAs + JLab LDRD
        • Collaboration with Theory on MCGen project DE-FOA-0002493 - preproposal submitted
        • Collaboration with BNL on AI scheduling DE-FOA-0002482
        • Collaboration with INDRA-ASTRA - ?
        • Collaboration with Sergey F. on AI + FPGA - deferred awaiting roadmap
        • Surrogate Models proposal (LDRD) - preproposal submitted
        • Amplitude Analysis Inverse Problem (LDRD) - preproposal submitted
    • Offsite Computing
      • OSG
      • NERSC, PSC, IU
  5. AOT


Minutes:

Attendees: Nathan B., Kishan R., Vardan G., Thomas B., Mike G., Torri J., Carl T.

  • Announcements
    • Fortnight paper: There was a suggestion that EPSCI group every focus group (AI, SRO, FPGA based data transfer, etc.) will come up with a paper that would benefit their research.
    • Summer internship program: 5 high school students will be working with our group during the June-July time frame.
  • Workshop and conferences
    • 3 accepted papers at VCHEP2021
    • TriDAS group will provide a presenter for the talk on TriDAS+JANA2 paper.
  • CI + SPACK
    • Summer intern (Jillian) will work on the JLAB common environment.
  • EIC
    • Graham informed on a new working group formation at the EIC, including David Lawrence, Christiano, and Dmitry Romanov.
    • Thomas reported that EIC will be able to submit jobs on OSG through newly created EIC sub VO on the JLAB OSG dedicated resources.
    • Brayan is going to increase fair share for the EIC VO, effectively treating EIC as a the 5th experimental Hall.
  • JANA2
    • Nathan continues working on JANA2 GlueX port, and reported a sizable progress achieved last week.
  • CLARA
    • v5.0.1 release is not officially deployed as a production version in CLAS12, so nothing to report.
  • EJFAT
    • ESnet whitebox design is available for review. The design includes an option for a switch based load balancing.
    • ESnet suggest using hardware switches equipped with the LAB protocol, where multiple links between two switches combine to provide higher bandwidth links between them.
    • PR is being prepared for the FPGA.
    • FPGA from the ESnet will be available for tests mid July.
  • Funding opportunities
    • Graham is leading multiple efforts to establish collaborations and projects with real funding opportunities, including an official collaboration with ESnet, ASCR funded 3 phase Data Reduction Pipeline project, and collaboration with BNL on AI model based workflows.
  • SRO
    • Ed sent Vardan detailed instructions how to operate the SAMPA setup.
    • Vardan was able to start the readout and record data from 5 front-end cards in 10 separate files (2 stream per card)..
    • Carl and Vardan are continuing to work on VTP and SAMPA setups in the indra-lab.
  • CODA
    • Carl is finalizing the EVIO-6 release
    • Vardan is working on JCEdit to implement FPGA based ROC, a new CODA component type.
  • AI
    • AI Experimental Controls
      • Torri is leading discussions at the AI WG weekly meetings related to defining critical design requirements and conditions for the project.
    • AICEG
      • Kishan continues to work with Nabuo on the AICEG project. He is evaluating Nabuo’s proposal to use a Lambda layer in the model that will help to incorporate user defined augmented features.
    • Hydra
      • Kishan he is trying to use layer-wise relevance propagation method to identify important sections of the histogram image.
      • Two summer interns will work on Hydra project this summer.
  • OSG
    • Thomas reported that the new feature to bundle similar jobs in the mc-wrapper is chocking CONDOR when the number of bundled jobs in the queue is higher than certain amount (>2000 or so). An obvious solution to this problem, according to Thomas, would be to introduce a limit on the number of jobs in the queue.
    • Two summer students/interns will work on mc-wrapper this summer.
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