Difference between revisions of "EJFAT EPSCI Meeting Sep. 27, 2023"
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(Created page with "The meeting time is 2:30pm. === Connection Info: === <div class="toccolours mw-collapsible mw-collapsed"> You can connect using [https://teams.microsoft.com/l/meetup-join/19%...") |
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# [https://ieeexplore.ieee.org/document/10046405 RT2022 Paper]: Submission Process Complete | # [https://ieeexplore.ieee.org/document/10046405 RT2022 Paper]: Submission Process Complete | ||
# [https://jeffersonlab.sharepoint.com/:b:/r/sites/SciComp/Shared%20Documents/EPSCI/EJFAT/EJFAT_ACAT_2022_QL_sub.pdf?csf=1&web=1&e=dR566P ACAT2022 Paper]: - submitted | # [https://jeffersonlab.sharepoint.com/:b:/r/sites/SciComp/Shared%20Documents/EPSCI/EJFAT/EJFAT_ACAT_2022_QL_sub.pdf?csf=1&web=1&e=dR566P ACAT2022 Paper]: - submitted | ||
− | # <s>CHEP 2023 Conference Publication | + | # <s>CHEP 2023 Conference Publication - Derek/Mike/Carl</s> Submitted |
− | # '''EJFAT Phase II | + | # '''EJFAT Phase II''' |
## Implementation details in the DAOS gateway. Specially when to keep track of how the FPGA would DMA event data cells in the future if it was a DAOS NIC card. ( Cissie ) | ## Implementation details in the DAOS gateway. Specially when to keep track of how the FPGA would DMA event data cells in the future if it was a DAOS NIC card. ( Cissie ) | ||
## Progress of multi FPGA and multi virtual LB control plane sw. ( Derek ) plus small features like authentication etc.. | ## Progress of multi FPGA and multi virtual LB control plane sw. ( Derek ) plus small features like authentication etc.. |
Latest revision as of 17:05, 27 September 2023
The meeting time is 2:30pm.
Connection Info:
You can connect using Teams Link. (Click "Expand" to the right for details -->):
Agenda:
- Previous meeting
- Announcements:
- NERSC Test Development:
- Data Source:
- JLAB, CLAS12, pre-triggered events - 1 channel
- Front End Packetizer pending mods for Tick-sync msg to CP - UDP packet to port on CP Host
- Data Sink:
- Perlmutter
- ERSAP
- Networking for Test
L3VPN Design with ESNetVet the cybersecurity controls with the security group.Implement Local network configuration changes/cybersecurity controlsConfigure L3VPN, establish peeringRelocate to HACS-4- Configure hosts to use tunnel, confirm traffic flow is as expected -
IPV4, IPV6 pending- Have IPv6 addresses - pending configuration
- Jumbo Frame availability thru ESnet network layers to LB
- JLab Preliminary NERSC Test
Vardan's Metrics/Horizontal Scaling- Using for CHEP Paper- Preliminary Testing: New LB f/w and CP:
JLab, ESnet- NERSC may be ready for connectivity test soon
- Test Plans - JLab, ESnet, NERSC:
- Data Source:
- Hall B CLAS12 detector streaming test
- Switch 7050 is expected to arrive some time around October; we have already transceivers, short cables and patch panel to connect up to 32 VTPs to it using two 10GBit links per VTP
- Fiber installation between hallb forward carriage and hallb counting room should be done this summer, will be enough for 24 VTPs using two 10GBit links per VTP
- We have only one fiber between hallb counting room and counting house second floor available right now, will order more fibers installation, may take several months
- There are several available fibers between counting house second floor and computer center (like 6), we can use a couple of them for our test
- Summary: sometime in October, we should have 48 10GBit links from 24 VTPs connected to the switch in hallb counting room, with that switch connected to computer center by 2x100GBit links
- Need to develop CONOPS with Streaming group (Abbott)
- LDRD Pending
- Targeting May 2024 during Beam downtime in Hall B
- Data Compressibility Studies using Hall B/D sample data
- RT2022 Paper: Submission Process Complete
- ACAT2022 Paper: - submitted
CHEP 2023 Conference Publication - Derek/Mike/CarlSubmitted- EJFAT Phase II
- Implementation details in the DAOS gateway. Specially when to keep track of how the FPGA would DMA event data cells in the future if it was a DAOS NIC card. ( Cissie )
- Progress of multi FPGA and multi virtual LB control plane sw. ( Derek ) plus small features like authentication etc..
- Progress of FPGA architecture ( Peter and Jonathan )
- Progress of finalizing a reassembly frame format ( Carl / Stacey )
- Demo Ready EJFAT Instance
- EJFAT Operational Status Board -> Prometheus Reporting
- Resources:
- AOT