EJFAT Group Meeting Oct. 12, 2023

The meeting time is 11:00am Eastern/USA.

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161 182 8967

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Agenda:

1. Previous meeting

2. Announcements:
3. NERSC Test Development:
   1. Data Source:
      1. JLAB, CLAS12, pre-triggered events - 1 channel
      2. Front End Packetizer pending mods for Tick-sync msg to CP - UDP packet to port on CP Host
   2. Data Sink:
      1. Perlmutter
      2. ERSAP
   3. Networking for Test
      1. IPv6 addresses pending configuration
      2. Jumbo Frame availability thru ESnet network layers to LB
      3. Ejfat-1 lacks L3-VPN connectivity
      4. /daqfs mounted on wrong subnet
   4. JLab Preliminary NERSC Test
      1. NERSC may be ready for connectivity test soon
      2. Dress Rehearsal
   5. Test Plans - JLab, ESnet, NERSC:
4. Hall B CLAS12 detector streaming test
   1. Switch 7050 is expected to arrive some time around October; we have already transceivers, short cables and patch panel to connect up to 32 VTPs to it using two 10GBit links per VTP
   2. Fiber installation between hallb forward carriage and hallb counting room should be done this summer, will be enough for 24 VTPs using two 10GBit links per VTP
   3. We have only one fiber between hallb counting room and counting house second floor available right now, will order more fibers installation, may take several months
   4. There are several available fibers between counting house second floor and computer center (like 6), we can use a couple of them for our test
   5. Summary: sometime in October, we should have 48 10GBit links from 24 VTPs connected to the switch in hallb counting room, with that switch connected to computer center by 2x100GBit links
   6. Need to develop CONOPS with Streaming group (Abbott)
   7. LDRD Pending
   8. Targeting May 2024 during Beam downtime in Hall B
   9. Data Compressibility Studies using Hall B/D sample data
5. RT2022 Paper: Submission Process Complete
6. ACAT2022 Paper: - submitted
7. CHEP 2023 Conference Publication
8. EJFAT Phase II
   1. Implementation details in the DAOS gateway. Specially when to keep track of how the FPGA would DMA event data cells in the future if it was a DAOS NIC card. ( Cissie )
   2. Flow Control
   3. Progress of multi FPGA and multi virtual LB control plane sw. ( Derek ) plus small features like authentication etc..
   4. Progress of FPGA architecture ( Peter and Jonathan )
   5. Progress of finalizing a reassembly frame format ( Carl / Stacey )
   6. Progress on software development for NVIDIA Bluefield2 DPU data steering from NIC to GPU memory ( Amitoj/Cissie )
   7. Progress on DAOS file-server OS and filesystem installation ( Amitoj/Cissie )
9. Demo Ready EJFAT Instance
10. EJFAT Operational Status Board -> Prometheus Reporting
11. Resources:
    1. HPDF
12. AOT

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