EJFAT EPSCI Meeting Oct. 25, 2023
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The meeting time is 2:30pm.
Connection Info:
You can connect using Teams Link. (Click "Expand" to the right for details -->):
Agenda:
- Previous meeting
- Announcements:
- NERSC Test Development:
- Data Source:
- JLAB, CLAS12, pre-triggered events - 1 channel
- Front End Packetizer pending mods for Tick-sync msg to CP - UDP packet to port on CP Host
- Data Sink:
- Perlmutter
- ERSAP
- Networking for Test
- Being finalized by Esnet/NERSC
- JLab Preps
- Finalizing application stack deployment on Permutter
- Standing up second JLab LB instance
- Test Plans - JLab, ESnet, NERSC:
- Data Source:
- Hall B CLAS12 detector streaming test
- Switch 7050 is expected to arrive some time around October; we have already transceivers, short cables and patch panel to connect up to 32 VTPs to it using two 10GBit links per VTP
- Fiber installation between hallb forward carriage and hallb counting room should be done this summer, will be enough for 24 VTPs using two 10GBit links per VTP
- We have only one fiber between hallb counting room and counting house second floor available right now, will order more fibers installation, may take several months
- There are several available fibers between counting house second floor and computer center (like 6), we can use a couple of them for our test
- Summary: sometime in October, we should have 48 10GBit links from 24 VTPs connected to the switch in hallb counting room, with that switch connected to computer center by 2x100GBit links
- Need to develop CONOPS with Streaming group (Abbott)
- LDRD Pending
- Targeting May 2024 during Beam downtime in Hall B
- Data Compressibility Studies using Hall B/D sample data
- RT2022 Paper: Submission Process Complete
- ACAT2022 Paper: - submitted
- CHEP 2023 Conference Publication
- EJFAT Phase II
- Implementation details in the DAOS gateway. Specially when to keep track of how the FPGA would DMA event data cells in the future if it was a DAOS NIC card. ( Cissie )
- Flow Control
- Progress of multi FPGA and multi virtual LB control plane sw. ( Derek ) plus small features like authentication etc..
- Progress of FPGA architecture ( Peter and Jonathan )
- Progress of finalizing a reassembly frame format ( Carl / Stacey )
- Progress on software development for NVIDIA Bluefield2 DPU data steering from NIC to GPU memory ( Amitoj/Cissie )
- Progress on DAOS file-server OS and filesystem installation ( Amitoj/Cissie )
- GPU purchase for EJFAT Test stand servers under IRIAD funds. The servers are capable of hosting 2 GPUs per server. ( Amitoj )
- Demo Ready EJFAT Instance
- EJFAT Operational Status Board -> Prometheus Reporting
- Resources:
- AOT