EJFAT EPSCI Meeting Mar. 20, 2024

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The meeting time is 2:30pm.

Connection Info:

You can connect using Teams Link. (Click "Expand" to the right for details -->): 

Meeting URL
	https://teams.microsoft.com/l/meetup-join/19%3ameeting_M2ExMzNiYmItNTNiMi00NzE4LTkwYWItOTQwYjJmMTJiMDhh%40thread.v2/0?context=%7b%22Tid%22%3a%22b4d7ee1f-4fb3-4f06-9037-2b5b522042ab%22%2c%22Oid%22%3a%22ff03cbe2-66d5-4741-bf32-ff1c69fa2fcc%22%7d

Meeting ID
273 279 114 915

Passcode
Rkypzi


Agenda:

  1. Previous meeting
  2. Announcements:
  3. 24th Real Time Conference – ICISE, Quy Nhon, Vietnam 22-26 April 2024 - Selected for 20 min Oral
    1. Show how EJFAT architecture contrasts with current
    2. Explain EJFAT's benefits to experimentalist
    3. Propose to measure/plot EJFAT event delivery elasticity/scaling through reassembly/reconstruction steps
    4. Use JLab-ESnet-NERSC/ORNL/JLab environment
    5. EJFAT configuration - CP current as of Jan 9 (ejfat-2 = Jun/2023, ejfat-5 = Feb/2024, ejfat-6 = March/2024 in the works)
  4. The first 100Gig circuit passing traffic to ESnet LB
  5. All EJFAT nodes have 48GB ramdisk, (ejfat-fs = 96GB)
  6. Cluster Activities:
    1. ejfat-1: Test moving a current LB install wholesale by moving files/containers
    2. ejfat-2: June 2023 LB - open for business
    3. ejfat-3: Ready to accept second FPGA for experimentation/install by ESnet
    4. ejfat-4: Carl's XDP experiments
    5. ejfat-5: Feb 2024 LB - latest production
    6. ejfat-6: Cissie's DAOS experiments / Mar 2024 LB - latest development
    7. ejfat-fs: Hosts NVME memory/disk
  7. NERSC Test Development:
    1. Data Source:
      1. JLAB, CLAS12, pre-triggered events - 1 channel
    2. Data Sink:
      1. Perlmutter
      2. ERSAP
    3. Networking for Test
      1. Currently 2 x 10 Gbps for JLab/L3 VPN - will expand to 200Gbps in near fututure
    4. Test Plans - JLab, ESnet, NERSC:
  8. ORNL/ESnet/JLab IRI Testbed (similar to NERSC) - Ross Miller <rgmiller@ornl.gov> project code CSC 266
  9. Hall B CLAS12 detector streaming test
    1. Switch 7050 is expected to arrive some time around October; we have already transceivers, short cables and patch panel to connect up to 32 VTPs to it using two 10GBit links per VTP
    2. Fiber installation between hallb forward carriage and hallb counting room should be done this summer, will be enough for 24 VTPs using two 10GBit links per VTP
    3. We have only one fiber between hallb counting room and counting house second floor available right now, will order more fibers installation, may take several months
    4. There are several available fibers between counting house second floor and computer center (like 6), we can use a couple of them for our test
    5. Summary: sometime in October, we should have 48 10GBit links from 24 VTPs connected to the switch in hallb counting room, with that switch connected to computer center by 2x100GBit links
    6. Need to develop CONOPS with Streaming group (Abbott)
    7. December 2023 Testing Activity
    8. SRO RTDP LDRD - need configuration for Spring '24 test with EJFAT
    9. Ready to supply up to 200 Gbps to EJFAT switch
  10. Demo Ready EJFAT Instance - Lower priority task
  11. EJFAT Operational Status Board -> ESnet Prometheus Reporting - Help Desk Ticket placed for JLab FW issue
  12. XDP sockets working (ejfat-4) - 50% less cpu, 3500 MTU limit
  13. Mtg with FEG/SRO - need long term solution for event sync
  14. RTDP - wants to use LB - some plumbing work reqd - ticket to provide 100Gbps from Indra/DAQ Lab (?)
  15. EJFAT Reconfig Design / PR - Funds available through end of March.
    1. Have ordered 22 PCIe VPI NICS
    2. Have ordered 5 OCP3/SFF VPI NICS
    3. Surrendering indra-s2; moving U280 to cluster
  16. EJFAT Phase II
    1. Implementation details in the DAOS gateway.
      1. Need to spec DAOS Use Cases ?
      2. Intel standing up special slack channel to discuss DAOS
      3. Connection Strategy to DAOS
      4. Specially when to keep track of how the FPGA would DMA event data cells in the future if it was a SmartNIC card. ( Cissie )
      5. daosfs01​ has 2 physical IB cards and can run 2 true engines with each CPU socket hosting one engine.
    2. Progress of multi FPGA and multi virtual LB control plane sw. ( Derek )
    3. Progress of FPGA architecture ( Peter and Jonathan )
      1. LB FW currently limited to 100 Gbps
      2. Reassembly work commencing soon
    4. Progress of finalizing a reassembly frame format (subordinate to 4.) ( Carl / Stacey )
    5. Progress on software development for NVIDIA Bluefield2 DPU data steering from NIC to GPU memory ( Amitoj/Cissie )
  17. Resources:
    1. HPDF
  18. AOT
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