Development Period - February 9-10

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Listed in order of suggested priority...

Re-measure emittance in order to analyze Run 1 conditions (3 hours)

  • February 9, 2015:
  • Identified parameters and details for a procedure
  • Measured emittance and Twiss for 6.3 MeV/c setup
  • Started emittance and Twiss for 5.5 MeV/c but harp is stuck so test deferred for now

Test hardware TOF veto at 31MHz (4 hours)

Test background as a function of target ladder position on large target foil (0 hours)

  • February 9, 2015:
  • Deferred until re-doing emittance measurement at 5.5 MeV/c to try for smaller spot size with 5 or 10 mm rings too

Test Mott delayed operation (1 hour):

  • Set of 6 runs while changing between No Delay and Delay=8
  • Runs 8218 - 8223 with 1.0 um gold foil
  • media:Delayed_Ana.pdf media:Delayed_Ana.pptx
  • A dump of first 10000 events from Run 8218 media:Hel_8218_0.txt shows that S1 helicity is lacking FADC by 0 to a few events. FADC helicity is correct because it is read event by event in the same module at the same time.
  • For the time being we will not run in delayed helicity mode because we cannot rely on S1. To use FADC helicity in delayed mode, decoder software development is required.

Test FADC time-of-flight readout and new Mott DAQ Configurations (2 hour)

  • February 4, 2015:
  • Added two more laser timing signals to FADC. From Disc 708, OUT signal was connected to FADC Ch10 and OUT_bar was connected to Ch12. The original laser timing signal is still connected to Ch9.
  • Run 8224 with 1.0 um gold foil and Mott_SemiInt configuration (31 MHz beam) (unfortunately, FADC threshold for Ch10 and Ch12 was left at 100)
  • Measure deadtime with 2.2 uA on 1 um gold foil:
  • Run 8225: Mott_SemiInt configuration (FADC+TDC+Scalers), Deadtime = 28% at 5.1 kHz.
  • Run 8227: SemiIntFast configuration (only readout of FADC, Blocklevel = 1) , Deadtime = 17% at 5.1 kHz.
  • Run 8228: SemiIntBlock configuration (only readout of FADC, Blocklevel = 50) , Deadtime = 1% at 5.1 kHz.
  1. Hai Dong may want to calculate a pedestal in front of NSB rather than at start of window (NOT relevant to the timing problem with a periodic signal).
  2. Hai Dong, with help from Bryan and Riad, will implement change FADC firmware to: Add an internal FADC delay=0-64 ns on Ch8, CH9, and Ch11 such that at least one channel readout has correct timing (signal starts below threshold in this channel). For these three channels, change pedestal to be average of 1 sample (because if any of the four samples used to get pedestal is above threshold, then calculations are no good - hence just use one sample).
  3. Riad will need to provide three laser timing signals: sine wave and two pulsed waves.
  4. Alexandre will provide Joe a PR for VME64x crate and Joe will purchase one.
  5. Next access will need to get JLab discriminator/scalars from tunnel.
  6. Alexandre and Riad will test JLab disc/scalars, to look at using blocking mode for both FADC/Scalar.
  7. Once we can reliably use FADC timing we will eliminate the dependence on external TDC.

Test Modification to FADC firmware, March 17, 2015

(Note that FADCPL was changed from 60 to 85 before Run 8302)

  • Mott Run 8312: Mott_SemiInt (FADC+TDC+Scalers), FADC Delay: Ch8=0,CH9=0,Ch11=4.
  • Mott Run 8313: Mott_SemiInt (FADC+TDC+Scalers), FADC Delay: Ch8=0,CH9=2,Ch11=4.
  • Mott Mott_Sample 8314, (FADC+TDC+Scalers), beam current = 0.9 uA.
  • Mott Mott_Sample 8315, (FADC+TDC+Scalers), beam current = 5.0 uA. Deadtime = 32% at 5.5 kHz.
  • Mott SampleBlock 8316, (only readout of FADC, Blocklevel = 50), beam current = 5.0 uA. Deadtime = 4% at 5.5 kHz.