Difference between revisions of "EJFAT Group Meeting Jan. 13, 2022"

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(Created page with " The meeting time is 11:00am. === Connection Info: === <div class="toccolours mw-collapsible mw-collapsed"> You can connect using [https://jlab-org.zoomgov.com/j/1610125238?p...")
 
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=== Minutes: ===
 
=== Minutes: ===
 
<ul>
 
<ul>
−
<li>A bug in the Xilinx 2020 tools was found responsible for checksum error in the P4 code; Esnet is migrating to the 2021 toolsand expects to refresh the U280 bitfile build in approx. 3 weeks.
 
−
<li>tcpdump can be used at the data sink in the interim
 
−
<li>Indra-s[123] machines will be used to EJFAT testing until further notice.
 
−
<li>Brent Morris / Networking doing PO for network equipment
 
−
<li>Compute Farm PO to be submitted 01/07/2022
 
−
<li>Need extended test plan/goals
 
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<li>ESnet participation ending in a few weeks (?)
 
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<li>Control Plane s/w support to be updated - sn-cli.c exemplar for C-based control plane
 
 
</ul>
 
</ul>
  

Revision as of 19:00, 11 January 2022

The meeting time is 11:00am.

Connection Info:

You can connect using ZoomGov Video conferencing (ID: 161 012 5238). (Click "Expand" to the right for details -->): 

Meeting URL
 https://jlab-org.zoomgov.com/j/1610125238?pwd=QnEvcjV6VFFndWZsQW15SmJKU0RJZz09&from=addon

Meeting ID
161 012 5238

Passcode
503371

Want to dial in from a phone?

Dial one of the following numbers:
US: +1 669 254 5252 or +1 646 828 7666 or +1 551 285 1373 or +1 669 216 1590 or 833 568 8864 (Toll Free)

Enter the meeting ID and passcode followed by #

Connecting from a room system?
Dial: bjn.vc or 199.48.152.152 and enter your meeting ID & passcode

Agenda:

  1. Previous meeting
  2. Issues for Discussion:
    • Status of P4 code update for packet checksum
    • Status of new bitfile for UDP-LB U280 FPGA
    • Status of Edge to Core Test Design
      • ERSAP / CLARA Data Generation for UDP-LB
      • UDP-LB Meta Data Insertion / Packetizer
      • UDP-LB Emulator
      • UDP-RE Source Data Protocol Termination / Reassembly
    • Feature List for host side FPGA:
      • Source Data protocol termination
      • Direct DMA to GPU
      • Transparent decompression / compression
    • Status of PO for Edge to Core Test Equipment
  3. AOT


Minutes:

Attendees:

  • M. S. Goodrich
  • D. Lawrence
  • Y. Kumar (ESnet)
  • S. Sheldon (ESnet)
  • C. Timmer
  • V. Gyurjyan
  • B. Hess
  • G. Heyes
  • A. Singh
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