ML-FPGA R&D for EIC

This is information related to beam tests done in support of the ML-FPGA R&D for EIC project.

Overview

The beam test will use a GEM detector and a small calorimeter behind one arm of the pair spectrometer in Hall-D. The setup will use two FPGA's, one for each detector, to process triggered data from the DAQ and send it into a JANA2 process. The downstream JANA2 process will run some algorithm on the data (proof-of-principle) and write the output to a file.

Meetings

• 2023-02-01
• 2023-01-18
• 2023-01-11
• 2022-12-12

Project Phases

Phase 1:

• Single detector readout (calorimeter)
• CDAQ, no FPGA
• JANA2 JStreamingEventSource with direct reading of TCP socket

Phase 2:

• Single detector readout (calorimeter)
• CDAQ, with FPGA
• JANA2 JStreamingEventSource with direct reading of TCP socket

Phase 3:

• Two detector readout
• CDAQ, with FPGA
• JANA2 JStreamingEventSource with direct reading of TCP socket, simple event building

Phase 4:

• Two detector readout
• CDAQ, with FPGA
• ERSAP backend with event building
• JANA2 algorithm
• ERSAP Event Recorder

Timetable of Activities

	Activity	start date	end date
step 1:	switch to cDAQ	2/6	2/8
step 2:	build events in cDAQ and send to Jana.	2/9	2/14
step 3:	TCP interface in FPGA (low speed - 1GB) and build events in FPGA	2/14	2/22
step 4:	send events from FPGA to Jana;	2/23	2/27
step 5:	work on NN processing in FPGA.	2/27	3/13
step 6:	send from FPGA to Jana : original and processed;	3/13	3/14
step 7:	continue work on ML FPGA algorithms and test new FPGA boards.	3/14	3/20

Useful links

• JANA4ML4FPGA GitHub repository
• Generic EIC-Related Detector R&D Program