Difference between revisions of "EJFAT EPSCI Meeting May. 8, 2024"
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(Created page with "The meeting time is 2:30pm. === Connection Info: === <div class="toccolours mw-collapsible mw-collapsed"> You can connect using [https://teams.microsoft.com/l/meetup-join/19%...") |
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### ERSAP | ### ERSAP | ||
## [https://docs.google.com/document/d/13VvyCMNJW3nIVZMgqOuPn3MBSLmfAl1zLkJAHw8fj04/edit?usp=drivesdk Test Plans - JLab, ESnet, NERSC:] | ## [https://docs.google.com/document/d/13VvyCMNJW3nIVZMgqOuPn3MBSLmfAl1zLkJAHw8fj04/edit?usp=drivesdk Test Plans - JLab, ESnet, NERSC:] | ||
− | ## '''100 Gbps / 25 - 40 Node Test''' | + | ## [http://jiriaf2301:3001/d/bdkbrakggnytcf/test?orgId=1 '''100 Gbps / 25 - 40 Node Test'''] |
# ORNL/ESnet/JLab IRI Testbed (similar to NERSC) - Ross Miller <rgmiller@ornl.gov> '''project code CSC 266''' | # ORNL/ESnet/JLab IRI Testbed (similar to NERSC) - Ross Miller <rgmiller@ornl.gov> '''project code CSC 266''' | ||
## Waiting on ORNL Internal Network Security | ## Waiting on ORNL Internal Network Security |
Latest revision as of 19:02, 8 May 2024
The meeting time is 2:30pm.
Connection Info:
You can connect using Teams Link. (Click "Expand" to the right for details -->):
Agenda:
- Previous meeting
- Announcements:
- System Status:
- NERSC Test Development:
- Data Source:
- JLAB, CLAS12, pre-triggered events - 1 channel
- Data Sink:
- Perlmutter
- ERSAP
- Test Plans - JLab, ESnet, NERSC:
- 100 Gbps / 25 - 40 Node Test
- Data Source:
- ORNL/ESnet/JLab IRI Testbed (similar to NERSC) - Ross Miller <rgmiller@ornl.gov> project code CSC 266
- Waiting on ORNL Internal Network Security
- ALS
- Socializing Experiment Agenda - In Review
- Hoping for First Runs Summer 2024
- JLab FEG/SRO - will use interim UDP solution for event sync
- EJFAT Reconfig meetings/Tools to explore options
- EJFAT Phase II
- Need long term solution for CP/Source event sync
- Implementation details in the DAOS gateway.
- Need to spec DAOS Use Cases ?
- Intel standing up special slack channel to discuss DAOS
- Connection Strategy to DAOS
- Specially when to keep track of how the FPGA would DMA event data cells in the future if it was a SmartNIC card. ( Cissie )
- daosfs01 has 2 physical IB cards and can run 2 true engines with each CPU socket hosting one engine.
- Progress of multi FPGA and multi virtual LB control plane sw. ( Derek )
- Progress of FPGA architecture ( Peter and Jonathan )
- LB FW currently limited to 100 Gbps
- Reassembly work commencing soon
- Progress of finalizing a reassembly frame format (subordinate to 4.) ( Carl / Stacey )
- Progress on software development for NVIDIA Bluefield2 DPU data steering from NIC to GPU memory ( Amitoj/Cissie )
- Resources:
- AOT