Difference between revisions of "EJFAT"
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<p>The FPGA resident LB aggregates data across all DAQ channels for a single discrete <span><em>tick</em></span> and routes this aggregated data to individual end compute nodes in cooperation with the FPGA host chassis CPU using algorithms designed for the host CPU and feedback received from the end compute node farm, maintaining complete opacity of the UDP payload to the LB (except for the LB meta-data).</p> | <p>The FPGA resident LB aggregates data across all DAQ channels for a single discrete <span><em>tick</em></span> and routes this aggregated data to individual end compute nodes in cooperation with the FPGA host chassis CPU using algorithms designed for the host CPU and feedback received from the end compute node farm, maintaining complete opacity of the UDP payload to the LB (except for the LB meta-data).</p> | ||
<h2 id="sec:data-pln">Data Plane (FPGA) Processing</h2> | <h2 id="sec:data-pln">Data Plane (FPGA) Processing</h2> | ||
| − | [[File:LB-data-pln.png|border|"Data Plane Flow | + | [[File:LB-data-pln.png|border|"Data Plane Flow Chart"]] |
<ul> | <ul> | ||
<li><p>Packet Parsing Stage</p> | <li><p>Packet Parsing Stage</p> | ||
Revision as of 19:53, 10 November 2021
Abstract
We describe a collaboration between Energy Sciences Network (ESnet) and Thomas Jefferson National Laboratory (JLab) for proof of concept engineering to program a Field Programmable Gate Array (FPGA) for network data routing of commonly tagged UDP packets to individual and configurable destination endpoints in a follow-on compute work load balanced manner, including some additional tagging for stream reassembly at the endpoint. The primary purpose of this FPGA based acceleration is to load balance work to destination compute farm endpoints with low latency and full line rate bandwidth of 100 Gbs with feedback (back-pressure) from the destination compute farm. ESnet used P4 programming on the FPGA to use meta-data in the UDP packet stream to route packets with a common tag to dynamically configurable endpoints controlled by the endpoint farm. Control plane programming tasks included back-pressure notifications from destination endpoints and notification processing by the FPGA host CPU to dynamically re-configure routing tables for the FPGA P4 code.
EJFAT Overview
This collaboration between ESnet and JLab for FPGA Accelerated Transport (EJFAT) seeks a network data transport capability to aggregate and dynamically route selected UDP traffic with endpoint feedback.
EJFAT will add meta-data to UDP data streams to be used both by the intervening FPGA, acting as a work Load Balancer (LB), to aggregate data packets from multiple logical input streams and dynamically route to endpoints and for an endpoint Reassembly Engine (RE) to perform custom reassembly resulting from network equipment fragmentation.
While the aggregation and routing meta-data included as the header in the payload is generic in design, it is being first utilized for streamed (non-triggered) data from the JLab DAQ to the back-end compute farm.
In the initial JLab deployment context, the FPGA will time-stamp aggregate across detector Data Acquisition System (DAQ) channels for the purpose of load balancing work to individual compute farm destinations in a farm status aware manner (see Figure [fig:ejfat] in Appendix [appendix:ejfat]), where work here is concerned with using data from an individual time-stamp across all DAQ channels to identify or reconstruct detector events.
This load balancing of computational work is under direct control of the compute farm via dynamic management of routing information communicated to the FPGA host CPU which is passed on to the FPGA.
As the aggregated/routed data is opaque to this design, it should be reusable for other data streams with aggregation/routing needs.
Read Out Controller Processing
The Read Out Controllers (ROC) of the JLab DAQ system will be enhanced to stream data via UDP and include new meta-data prepended to the original payload that serves the needs of the compute destination LB and the destination fragmentation RE. Figure [fig:roc] is a diagram of the new data stream processing requirements for the JLaB DAQ system.
This new meta-data, populated by the JLab DAQ system, consists of two parts, the first for the LB and the second for the RE.
Load Balancer Meta-Data
The LB meta-data (Figure [fig:roc], cyan section) is 96 bits that in order consists of
is 32 bits (bits 0-31) such that
bits 0-7 ASCII character ’L’
bits 8-15 ASCII character ’B’
bits 16-23 LB version number starting at 1 (constant for run duration)
bits 24-31 Protocol Number (very useful for protocol decoders e.g., wireshark/tshark )
(Time stamp or proxy) is a 64 bit quantity (bits 32-95) that for a DAQ run duration
Monotonically increases
Unique
Never rolls over
Never resets
Serves as a common tag across multiple DAQ ROC channels/packets related to the same time-stamped data transfer.
In standard IETF RFC format:
protocol 'L:8,B:8,Version:8,Protocol:8,Tick:64' 0 1 2 3 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | L | B | Version | Protocol | +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | | + Tick + | | +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
Reassembly Engine Meta-Data
The RE meta-data (Figure [fig:roc], yellow section) is 64 bits and consists of
bits 0-3 Version number
bits 4-13 Reserved
bit 14 indicates first packet
bit 15 indicates last packet
bits 16-31 ROC Id
bits 32-63 packet sequence number or optionally data offset byte number for reassembly
In standard IETF RFC format:
protocol 'Version:4,Rsvd:10,First:1,Last:1,ROC-ID:16,Offset:32' 0 1 2 3 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ |Version| Rsvd |F|L| ROC-ID | +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | Offset | +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
The resultant DAQ data stream is shown just below the block diagram in Figure [fig:roc] and depicts the stream UDP packet structure from the DAQ system to the LB. Individual packets are meta-data tagged both for the LB, to route based on tick to the proper compute node, and for the RE with packet offset spanning the collection of packets for a single tick for eventual destination reassembly.
The depicted sequence is only illustrative, and no assumption about the order of packets with respect to either tick or offset should be made by the LB or the RE.
UDP Header
The UDP Header will be populated as follows:
: lower 16 bits of Load Balancer Tick (for LAG switch entropy)
: Value that indicates LB should perform load balancing (else packet is discarded)
The resultant DAQ data stream is shown below the block diagram and depicts the stream UDP packet structure. Individual packets
ROC Aggregation Switch
Individual ROC channels will be aggregated for maximum throughput by a switch using Link Aggregation Protocol (LAG) or similar where the network traffic downstream of the switch will be addressed to the LB FPGA (see (Figure [fig:ejfat], Appendix [appendix:ejfat]).
If the LAG configured switch proves to be incapable of meeting line rate throughput (100Gbs), then an additional FPGA(s) can be engineered to subsume this function as depicted in Figure [fig:roclag].
LB Processing
The FPGA resident LB aggregates data across all DAQ channels for a single discrete tick and routes this aggregated data to individual end compute nodes in cooperation with the FPGA host chassis CPU using algorithms designed for the host CPU and feedback received from the end compute node farm, maintaining complete opacity of the UDP payload to the LB (except for the LB meta-data).
Data Plane (FPGA) Processing
Packet Parsing Stage
Headers defined in the previous stage will be parsed and made available for the remaining stages.
The Event Payload MUST NOT be parsed by the load balancer.
Input Packet Filter Stage
Implemented as a P4 table with the following properties
Max Entries: 32
Key:
(Exact Match) EtherType
(Exact Match) (96b 0 ∥ IPv4 Dst) OR IPv6 Dst
(Binary Match) UDP Dst Port
Value: None
A miss in this table MUST result in the packet being discarded since it is not intended for the load balancer.
The P4 code in this stage must also check both the Magic and Version fields in the LB Header. A mismatch from the expected values MUST result in the packet being discarded.
Calendar Epoch Assignment Stage
Implemented as a P4 table with the following properties
Max Entries: 128
Key: (Ternary Match) 64b LB Event Number (Timestamp)
Value: 32b Calendar Epoch
Load Balance Calendar to Member Map Stage
Implemented as a P4 table with the following properties
Max Entries: 2048
Key:
(Exact Match) 32b Calendar Epoch
(Exact Match) 9b Calendar Slot (ie. LB Event Number & 0x1FF)
Value: 16b LB Member ID
Load Balance Member Info Lookup Stage
Implemented as a P4 table with the following properties
Max Entries: 1K
Key:
(Exact Match) 16b EtherType (IPv4 or IPv6)
(Exact Match) 16b LB Member ID
Value:
8b Action ID
1 = IPv4 Rewrite
2 = IPv6 Rewrite
IPv4 Rewrite Action
48b MAC DA (for next-hop router)
32b IPv4 Dst
16b UDP Dst Port
IPv6 Rewrite Action
48b MAC DA (for next-hop router)
128b IPv6 Dst
16b UDP Dst Port
Rewrite Action type must match the input packet’s EtherType. E.g. An Input IPv4 packet cannot use the IPv6 Rewrite Action and vice versa.
Before applying the rewrite actions, the original packet’s MAC DA should be copied into the MAC SA. This will ensure that the outgoing packet will be sent from exactly the MAC address that the original packet was destined to. This will help to keep the MAC FDB entries in the adjacent switches from expiring.
Packets will be transmitted back out the port they were received on.
The resultant LB data stream is shown just above the block diagram in Figure [fig:lb] and depicts the stream UDP packet structure from the LB to the RE concerning an arbitrary single destination compute node. Individual packets here are still meta-data tagged both for the LB and RE. The RE for a target compute node will see a collection of packets that share a common tick.
The depicted sequence is only illustrative, and no assumption about the order of packets with respect to the offset should be made by the RE.
Control Plane (Host CPU) Processing
[fig:cpfc]Control Plane Flow Chart
Software Initialization Steps
PROPOSAL: A low-level C Software library will be provided to allow insertion/deletion of table entries into each of the P4 tables. All other SW will likely need to be written by the user of the LB pipeline.
Populate Input Packet Filter Table
Table Insert ⟨0x800, LB IPv4 Addr, LB UDP Dst⟩
Table Insert ⟨0x86dd, LB IPv6 Addr, LB UDP Dst⟩
Populate Load Balance Member Table: For each LB Member
Allocate next free Member ID number from SW pool
Table Insert
K: ⟨0x800, Member ID⟩
V: ⟨IPv4 Rewrite, 0, Next-Hop MAC DA, Worker IPv4 Dst, Worker UDP Dst Port⟩
Table Insert
K: ⟨0x86dd, Member ID⟩
V: ⟨IPv6 Rewrite, 0, Next-Hop MAC DA, Worker IPv6 Dst, Worker UDP Dst Port⟩
Populate Load Balance to Member Map Table
Allocate next free Calendar Epoch number from SW pool
Assign all active LB Member IDs to the 512 Calendar Slots
Any members can occur between 0-512 times in the calendar
A member occurring more times in the calendar has a higher “weight” and will be more likely to be assigned an event within this Calendar Epoch
All 512 slots MUST have a member assigned to them or events that target the empty slot will be entirely discarded by the load balancer
For each Calendar Slot Table Insert
K: ⟨Calendar Epoch, Calendar Slot⟩
V: ⟨LB Member ID⟩
Populate the Calendar Epoch Assignment Table
Assign all Event IDs (Timestamps) to the newly allocated Calendar Epoch
Table Insert
K: ⟨*⟩
V: ⟨Calendar Epoch⟩
The load balancer will now assign each Rx’d packet to exactly one of the LB members based on the Event ID contained in the packet. The mapping will remain consistent for any given Event ID within an Epoch since the Calendar and Member tables cannot change within a given Epoch.
Making Changes to the Load Balancer Configuration
This section assumes that the load balancer is in-service and as such, care must be taken to avoid service disruption during reconfiguration. If the load balancer is out-of-service, you can reconfigure it using the Initialization steps above without care for disruption.Any Epoch that is reachable (connected) via the Calendar Epoch Assignment table MUST not be changed. In-service reconfiguration of the load balancer is done by the following steps.
Allocate the next free Calendar Epoch ID: Once we’re done all the rest of the updates, we’ll activate this new Epoch
Insert new entries into the Load Balance Member Table for any entries that need to be different in the next Epoch
Compute and insert an entirely new calendar into the Load Balance to Member Map Table using the next Calendar Epoch ID
Choose an Event ID in the (near) future which will become the boundary between the current Epoch and the new Epoch.
Compute a set of Ternary prefix matches over the Event ID space which describe the entire range of Event IDs from the start of the current Epoch up to the start of the new Epoch.
Program the ternary prefix matches into the Calendar Epoch Assignment Table
Update the wildcard match in the Calendar Epoch Assignment Table to point to the new Epoch
The new Epoch is activated and MUST NOT be changed
After waiting an appropriate time for all events from the previous Epoch to have quiesced, perform the following cleanup steps.
Delete the ternary prefix matches for the previous Epoch from the Calendar Epoch Assignment Table. This disconnects all references for the previous Epoch to the rest of the pipeline tables.
Delete the Calendar for the previous Epoch
Delete the Member rewrites for the previous Calendar
[fig:lb]Load Balancer/Host CPU Processing
Reassembly Engine Processing
Time-Stamp aggregated data transferred through network equipment will be fragmented and require reassembly by the RE on behalf of the targeted compute farm destination node. Several candidate designs are being considered as depicted in Figure [fig:reass]:
RE resident () in each compute node in an FPGA accelerated Network Interface Card (NIC) (e.g., Xilinx SN1000)
RE resident () in each compute node CPU operating system.
RE centralized () in an FPGA residing in a compute farm switch.
Additionally, end compute nodes are individually responsible for informing the LB host CPU of status such that the LB host CPU can make informed decisions in comprising an effective load balancing strategy for the FPGA resident LB.
[fig:reass]Compute Farm Reassembly/Feedback
Initial Test Configuration
Figure [fig:tst0] depicts a notional EJFAT initial test configuration using commonly available Unix utilities and not initially using a network switch. The sequence of this test configuration is as follows:
Generate a representative ROC PCAP file using the script in section [sec:rocpcap]. This data should emulate a data stream from the DAQ system exhibiting desired sequences in the stream that will test the functionality of the LB.
Configure the LB P4 load balancer per the guidelines set forth in section [sec:lbcntrlpln].
Use tcpreplay to send the ROC PCAP file via the test host CPU NIC into the FPGA resident LB via the FPGA’s (bidirectional) QSFP28 optical port.
Use tcpdump to capture the LB response sent back into the test host CPU NIC into an LB PCAP file
Use Wireshark/tshark or other to decode, render, and examine the LB PCAP file to ascertain if the LB provided the correct response. Decoding should be facilitated by using the Protocol field in the LB meta-data specified in section [sec:Load Balancer Meta-Data] with add-ins for the bit structures defined in sections [sec:Load Balancer Meta-Data], [sec:Reassembly Engine Meta-Data].
Use an LB config process running on the host CPU to setup test conditions with the destination compute farm to alter the LBs routing strategy using the information in sections [sec:cntrl-pln], [sec:lbcntrlpln].
[fig:tst0]EJFAT Test Configuration
LB Data Plane P4 Code
line 12: These are understood to be MAC addresses
line 45: IPV4 options length = (ipv4 × hdrlen - 5) × 32
line 56: literally “LB” = 0x4c42; c.f. section [sec:Load Balancer Meta-Data] and line 8 section [sec:rocpcap].
line 57: LB version; c.f. line 9 section [sec:rocpcap]
line 58: protocol; c.f. line 10 section [sec:rocpcap], section [sec:roc]
line 150, 301: Gate to ensure in packet is for LB
line 174: epoch is determined by largest prefix match of tick; c.f. section [sec:lbcntrlpln] lines 18,25 for epochs 0,1 respectively
line 185: lower 9 bits of tick used for member slot indexing on round-robin basis; all 512 member slots require population for all active epochs; c.f. line 33 section [sec:lbcntrlpln]
LB Control Plane
This is the Vivado P4 simulator control plane configuration script:
lines 1,8: Sets the LB MAC address, IP address for IPV4, IPV6 respectively.
line 15: Set up Epoch 0 to match all ticks at low priority (=64)
line 22: Set up Epoch 1 to match ticks for which the 2nd least significant nibble=1 and the most significant nibble is arbitrary designating 16 possible tick values for Epoch 1 at higher priority (=5).
line 29: Designate member (end-node) 0 for calendar slot 0xa, Epoch 0
line 36: Designate member (end-node) 0 for calendar slot 0x14, Epoch 1
line 43: Designate member 0 for IPV4 packets as MAC=0x11223344556, IP=0xaabbccdd, Port=0x4556
line 52: Designate member 0 for IPV6 packets as MAC=0x11223344556,
IP=0xfe8000000000000000000000000000, Port=0x4556
ROC PCAP Generator Script
The following Scapy test script can be used to generate the ROC PCAP file shown in Figure [fig:tst0]:
Scapy Installation
Scapy may be installed by executing the following command at the Unix command line:
pip3 install --user scapy
ROC PCAP Meta Data File
In the following file:
Each row (1...n) in this file matches with the corresponding packet (1...n) in the packets_in.pcap file. ( Lines 42, 46 in section [sec:rocpcap] )
The simulator loads a line from this file and uses it to initialize the short_metadata struct which is processed along with the corresponding packet data.
You should find references to “short_metadata” struct in the p4 program.
I have no idea what the sim does when it has more packets in the .pcap file than the number of lines in the .meta file. In general, all of these fields may be relevant. For the load balancer specifically, the only field that matters is really the “egress_spec” field. On the way in, it contains the *ingress* port. It isn’t touched by the p4 program since we always want the output packet to go back out the exact same interface that it arrived on (after we rewrite the destination header fields of course).
The p4bm simulator does something like this:
open packets_in.pcap for read
open packets_in.meta for read
open packets_out.pcap for write
open packets_out.meta for write
while (!done) {
read packet p from packets_in.pcap
read metadata row m from packets_in.meta
(out_packet, out_meta) = simulate_the_p4(p, m)
write out_packet to packets_out.pcap
write out_meta to packets_out.meta
The pcap-generator.py script isn’t directly used by the p4bm sim. That’s just something I wrote to help you to make up input packets for the simulator so you didn’t have to make your input packets (as seen in packets_in.pcap) by hand.
There is a 1:1 correspondence between calls to write_packet() in the pcap-generator.py script and packets in the packets_in.pcap file.
The .py program spits out 2 interleaved ROC transfers (one transfer is carried in IPv4, the other is in IPv6). Each ROC transfer starts out as 1050 bytes of EVIO6 data. It is then segmented into 100 byte segments, ready to be put into a packet. Each segment gets a EVIO6 Segmentation header added to keep track of which segment it is, then each segment gets a UDP Load Balancer header added to give the load-balancer its context.
Each call to write_packet() spits out one of the segments in either a IPv4 or IPv6 encapsulation.
The program might be more clear if you were to duplicate the loop (one loop for IPv4 and one loop for IPv6) and put a single call to write_packet() in each of the loops. That might make it more clear that it was 2 transfers since they would no longer be interleaved.
The 2 lines in packets_in.meta will be used for the first 2 packets in the packets_in.pcap file. As currently written, one of those lines will be for the first segment in IPv4 and the second line will be for the first segment in IPv6. As I mentioned before, I’m actually not certain what happens after that in the simulator. In practice, it shouldn’t be important for this pipeline since it doesn’t get modified by the p4 program at all.
Tshark Plug-in for LB Meta-Data
In the following file:
Tshark Plug-in for Payload Seg
In the following file:
99
Author, A.N and Another, A. N., 2010, MNRAS, 431, 28.
Appendix: EJFAT Processing
[fig:ejfat]EJFAT Load Balanced Transport.
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