Difference between revisions of "Tritium DAQ page VME crate config"
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Line 4: | Line 4: | ||
{| class="wikitable" style="text-align: center; width: 400px; height: 200px;" | {| class="wikitable" style="text-align: center; width: 400px; height: 200px;" | ||
− | !slot # | + | !slot #!!1!!2!!3!!4!!5!!6!!7!!8!!9!!10!!11!!12 |
|- | |- | ||
− | |'''Module''' ||CPU | + | |'''Module''' ||CPU || TI || SD 8th Expansion || SD Board || FADC || FADC || FADC || FADC || FADC || FADC || FADC || FADC |
|- | |- | ||
− | |'''islot ''' || - | + | |'''islot ''' || - || - || - || - || 0 || 1 ||2 || 3 ||4 || 5 || 6 || 7 |
|- | |- | ||
− | |'''Input Signals''' | + | |'''Input Signals''' || - || - || - ||- || Cer, S0 || S2L || S2R || BPM, Raster, PRL1-16,33, PRL2-16,33 || PRL1 0-15 || PLR1 17-32 || PRL2 0-15|| PRL2 17-32 |
|- | |- | ||
− | |'''Module info''' ||halladaq8 | + | |'''Module info''' ||halladaq8 || - || - || - || - || - ||-|| - || - || - || - || - |
|} | |} | ||
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{|class="wikitable" style="text-align: center; width: 400px; height: 200px;" | {|class="wikitable" style="text-align: center; width: 400px; height: 200px;" | ||
− | !slot #!!13!!14!!15!!16!!17!!18!!19!!20 | + | !slot #!!13!!14!!15!!16!!17!!18!!19!!20!!21 |
|- | |- | ||
− | |'''Module''' || | + | |'''Module''' || Blank || F1 SD || Blank || F1 TDC || Blank || F1 TDC || Blank || ECL Splitter || MLU |
|- | |- | ||
− | |'''Module info''' || -|| - || - || -|| - || | + | |'''Module info''' || -|| - || - || -|| - ||- || -|| - || v1495 |
|- | |- | ||
− | |'''Input Signals''' || S2L&Cer&S0 || - || Trig & S2R | + | |'''Input Signals''' || - || - || - || S2L&Cer&S0 || - || Trig & S2R || - || - || - |
|} | |} | ||
Line 30: | Line 30: | ||
{|class="wikitable" style="text-align: center; width: 400px; height: 200px;" | {|class="wikitable" style="text-align: center; width: 400px; height: 200px;" | ||
− | !slot # | + | !slot #!!1!!2!!3!!4!!5!!6!!7!!8!!9!!10!!11!!12!!13!!14!!15!!16!!17!!18!!19!!20!!21 |
|- | |- | ||
|'''Module''' ||CPU || Empty || TI || Empty || SD Board || FADC || FADC || FADC || FADC || FADC || Empty || F1 SD || Blank || F1 TDC || Blank || F1 TDC || Blank || MLU || ECL Splitter || Flex-IO || Blank | |'''Module''' ||CPU || Empty || TI || Empty || SD Board || FADC || FADC || FADC || FADC || FADC || Empty || F1 SD || Blank || F1 TDC || Blank || F1 TDC || Blank || MLU || ECL Splitter || Flex-IO || Blank |
Revision as of 11:05, 4 September 2018
Left HRS
Configuration since Aug 01 2018 (VME crate 31)
slot # | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 |
---|---|---|---|---|---|---|---|---|---|---|---|---|
Module | CPU | TI | SD 8th Expansion | SD Board | FADC | FADC | FADC | FADC | FADC | FADC | FADC | FADC |
islot | - | - | - | - | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
Input Signals | - | - | - | - | Cer, S0 | S2L | S2R | BPM, Raster, PRL1-16,33, PRL2-16,33 | PRL1 0-15 | PLR1 17-32 | PRL2 0-15 | PRL2 17-32 |
Module info | halladaq8 | - | - | - | - | - | - | - | - | - | - | - |
slot # | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 |
---|---|---|---|---|---|---|---|---|---|
Module | Blank | F1 SD | Blank | F1 TDC | Blank | F1 TDC | Blank | ECL Splitter | MLU |
Module info | - | - | - | - | - | - | - | - | v1495 |
Input Signals | - | - | - | S2L&Cer&S0 | - | Trig & S2R | - | - | - |
Configuration prior July 17 2018 (VME crate 31)
slot # | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Module | CPU | Empty | TI | Empty | SD Board | FADC | FADC | FADC | FADC | FADC | Empty | F1 SD | Blank | F1 TDC | Blank | F1 TDC | Blank | MLU | ECL Splitter | Flex-IO | Blank |
Module info | intelha3 - switched to halladaq8 in March | - | - | - | - | ACDI 762 | ACDI 786 | ACDI 201 | ACDI 420 | ACDI 809 | - | - | - | - | - | - | - | 1495 | - | - | - |
Input Signals | - | - | - | - | - | S2L | S2R | Cer&S0&Ref. | Raster | ? | - | - | S2L&Cer&S0 | - | Trig & S2R | - | - | - | - | - |