Data Acquisition System and Triggers

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Overview

(see Tritium DAQ page)

Trigger Checkout Plan (Experts Only)

In general, we need one hall access if everything works fine.

Step 1

1. Use remote scopes with inputs S0 (from FIFO), S2 (from FIFO), GC (from FIFO), S0&S2 (from Logic Unit) and S0||S2 (from Logic Unit)
2. Verify that the S0 and S2 signals are as they should be (see picture (needs to be added!!!))
3. Verify that the S0&&S2 signal is within the GC signal with the desired time distance (see picture (needs to be added!!!))
4. Verify that the S0||S2 signal is within the GC signal with the desired time distance. Take also into account the extra cable delay from the S0|S2 logic unit to the (S0||S2)&&GC logic unit (see picture (needs to be added!!!))
   • NOTE: The S0&&S2 and S0||S2 times could be also estimated from the S0 and S2 signals with the known delays from the trigger schematics if there is no remote scope available for the RHRS.
5. If necessary go to the hall and change individual trigger delays!

• In parallel: Check S0, S2 and GC timings with Tong's and Jason's scripts.

Step 2

1. Go to the hall and plug in the trigger signals and S2 on the 4-channel scopes.
2. Check the individual trigger delays with respect to each and other and S2 (leads the time for S0&S2 and S0&S2&GC). Keep in mind to take also into account different cable length of the triggers from the logic unit to the TS input.
3. If necessary go to the hall and modify the cables.

• In parallel: Check trigger time distributions with Shujie's script.

FADC Check

1. Modify FADC readout list to switch to raw sample mode:
   LHRS:
   • on adaq@adaq1:
   • "ssh -Y dvcs@intelha3"
   • "cd fadc_mike/BlkRead"
   • open "roc31_tritium_list.c"
   • change "FADC_MODE" to "10"; save and exit;
   • "make"
     RHRS:
     • on adaq@adaq2:
     • "ssh -Y adaq@halladaq8"
     • "cd tritium_fadc/BlkRead/"
     • open "roc20_tritium_list.c"
     • change "FADC_MODE" to "10"; save and exit;
     • "make"

ReDownload coda;

Check the ROC31/ROC20 coda window to make sure it's in mode 10;

Take runs;

1. Decode a run with FADC decoder:
2. gotritium; cd scripts/FADC_decode;
3. ./FADCcom

check /chafs1/work1/tritium/FADC_rootfiles/fadc_*.root. Any under/overflow? Is signal 15 samples away to the window beginning?

Also there is a txt in scripts/FADC_decode/results. Make sure all the overflow/underflow/bad pedestal are 0 percent for slot 6, 7, 8 (LHRS), and slot 13, 14, 15(RHRS);