Difference between revisions of "Tritium DAQ page F1VETROCmap"

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{| border="1"
 
{| border="1"
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!F1 VME Slot!!F1 channel!!Signal
+
!Signal!!F1 VME Slot!!F1 channel
 
|-
 
|-
 
| S2L-1 || 14 || 0  
 
| S2L-1 || 14 || 0  
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{| border="1"
 
{| border="1"
−
!F1 VME Slot!!F1 channel!!Signal
+
!Signal!!F1 VME Slot!!F1 channel
 
|-
 
|-
 
|-
 
|-
−
| 16 || 0 || T1
+
| T1 || 16 || 0  
 
|-
 
|-
−
| 16 || 1 || T2
+
| T2 || 16 || 1  
 
|-
 
|-
−
| 16 || 2 || T3
+
| T3 || 16 || 2  
 
|-
 
|-
−
| 16 || 3 || (nothing)
+
| (nothing) || 16 || 3  
 
|-
 
|-
−
| 16 || 4 || S0 OR S2 RHRS
+
| S0 or S2 RHRS || 16 || 4  
 
|-
 
|-
−
| 16 || 5 || L1A_remote
+
| L1A_remote || 16 || 5  
 
|-
 
|-
−
| 16 || 6 || clock RHS
+
| clock RHRS || 16 || 6  
 
|-
 
|-
−
| 16 || 7 || clock LHRS
+
| clock LHRS || 16 || 7  
 
|-
 
|-
−
| 16 || 8 || Shower Sum
+
| Shower Sum || 16 || 8  
 
|-
 
|-
−
| 16 || 9 || S0 or S2 LHRS
+
| S0 or S2 LHRS || 16 || 9  
 
|-
 
|-
−
| 16 || 10 || S2 left
+
| S2 left || 16 || 10  
 
|-
 
|-
−
| 16 || 11 || S2 right
+
| S2 right || 16 || 11  
 
|-
 
|-
−
| 16 || 12 || S0 or S2 RHRS
+
| S0 or S2 RHRS || 16 || 12  
 
|-
 
|-
−
| 16 || 13 || all adc gate
+
| all adc gate || 16 || 13  
 
|-
 
|-
−
| 16 || 14 || L1A
+
| L1A || 16 || 14  
 
|-
 
|-
−
| 16 || 15 || RF signal
+
| RF signal || 16 || 15  
 
|-
 
|-
−
| 16 || 16 || S2R-1
+
| S2R-1 || 16 || 16
 
|-
 
|-
 
| : || : || :
 
| : || : || :
 
|-
 
|-
−
| 16 || 31 || S2R-16
+
| S2R-16 || 16 || 31
 
|}
 
|}

Revision as of 10:13, 8 December 2017

Channel maps for F1TDCs and VETROC

Right HRS

Configuration valid starting from run 90465 (December 5, 2017):

Signal F1 VME Slot F1 channel VETROC channel
T-1 8 0 112
T-2 8 1 113
T-3 8 2 114
T-4 8 3 115
T-5 8 4 116
T-6 8 5 117
RHRS clock 8 6 118
LHRS clock 8 7 119
L1A_R 8 8 120
RHRS clock 8 9 121
S2L 8 10 122
S2R 8 11 123
S0 or S2 8 12 124
ADC gate 8 13 125
RF time 8 14 126
L1A 8 15 127
S2L-1 8 16 48
: : : :
S2L-16 8 31 63
Signal F1 VME Slot F1 channel VETROC channel
GC-01 10 0 96
: : : :
GC-10 10 9 105
GC_SUM 10 10 106
S0A 10 11 107
S0B 10 12 108
S0coin 10 13 109
L1A 10 14 110
S2coin 10 15 111
S2R-1 10 16 32
: : : :
S2R-16 10 31 47

Left HRS

Configuration valid starting from run 675 (December 5, 2017):

Signal F1 VME Slot F1 channel
S2L-1 14 0
: : :
S2L-16 14 15
CER-1 14 16
: : :
CER-10 14 25
GC SUM 14 26
S0A 14 27
S0B 14 28
S0coin 14 29
L1A 14 30
S2 14 31
Signal F1 VME Slot F1 channel
T1 16 0
T2 16 1
T3 16 2
(nothing) 16 3
S0 or S2 RHRS 16 4
L1A_remote 16 5
clock RHRS 16 6
clock LHRS 16 7
Shower Sum 16 8
S0 or S2 LHRS 16 9
S2 left 16 10
S2 right 16 11
S0 or S2 RHRS 16 12
all adc gate 16 13
L1A 16 14
RF signal 16 15
S2R-1 16 16
: : :
S2R-16 16 31
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