Difference between revisions of "Tritium DAQ page F1VETROCmap"

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Line 111: Line 111:
 
!VME Slot!!channel!!Signal
 
!VME Slot!!channel!!Signal
 
|-
 
|-
 +
| 10 || 1 || GC-01
 
|-
 
|-
| 10 || 0 ||  
+
| : || : || :
|-
 
| 10 || 1 || S0A
 
 
|-
 
|-
| 10 || 2 || S0B
+
| 10 || 10 || GC-10
 
|-
 
|-
| 10 || 3 || S0coin
+
| 10 || 11 || GC-SUM
 
|-
 
|-
| 10 || 4 || L1A
+
| 10 || 12 || S0A
 
|-
 
|-
| 10 || 5 || S2
+
| 10 || 13 || S0B
 
|-
 
|-
| 10 || 3 || S0coin
+
| 10 || 14 || S0coin
 
|-
 
|-
| 10 || 4 || L1A
+
| 10 || 15 || RF time
 
|-
 
|-
| 10 || 5 || S2
+
| 10 || 16 || S2coin
 
|-
 
|-
| 10 || 16 || S2R-1
+
| 10 || 17 || S2R-1
 
|-
 
|-
 
| : || : || :
 
| : || : || :
 
|-
 
|-
| 10 || 31 || S2R-16
+
| 10 || 32 || S2R-16
 
|}
 
|}

Revision as of 15:20, 6 December 2017

Channel maps for F1TDCs and VETROC

Left HRS

Configuration valid starting from run 675 (December 5, 2017):

VME Slot channel Signal
14 0 S2L-1
: : :
14 15 S2L-16
14 16 CER-1
: : :
14 25 CER-10
14 26 GC SUM
14 27 S0A
14 28 S0B
14 29 S0coin
14 30 L1A
14 31 S2
VME Slot channel Signal
15 0
15 1 S0A
15 2 S0B
15 3 S0coin
15 4 L1A
15 5 S2
15 3 S0coin
15 4 L1A
15 5 S2
15 16 S2R-1
: : :
15 31 S2R-16

Right HRS

Configuration valid starting from run 90465 (December 5, 2017):

VME Slot channel Signal
8 1 T-1
8 2 T-2
8 3 T-3
8 4 T-4
8 5 T-5
8 6 T-6
8 7 RHRS clock
8 8 LHRS clock
8 9 L1A_R
8 10 RHRS clock
8 11 s2L
8 12 s2R
8 13 s0_or_S2
8 14 ADC gate
8 15 L1A
8 16 S2L-1
: : :
8 31 S2L-16
VME Slot channel Signal
10 1 GC-01
: : :
10 10 GC-10
10 11 GC-SUM
10 12 S0A
10 13 S0B
10 14 S0coin
10 15 RF time
10 16 S2coin
10 17 S2R-1
: : :
10 32 S2R-16