Difference between revisions of "Tritium DAQ page F1VETROCmap"

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{| border="1"
 
{| border="1"
!F1 VME Slot!!F1 channel!!Signal
+
!Signal!!F1 VME Slot!!F1 channel!!VETROC channel
 
|-
 
|-
| 8 || 0 || T-1
+
T-1 || 8 || 0 || 112
 
|-
 
|-
| 8 || 1 || T-2
+
T-2 || 8 || 1 || 113
 
|-
 
|-
| 8 || 2 || T-3
+
T-3 || 8 || 2 || 114
 
|-
 
|-
| 8 || 3 || T-4
+
T-4 || 8 || 3 || 115
 
|-
 
|-
| 8 || 4 || T-5
+
T-5 || 8 || 4 || 116
 
|-
 
|-
| 8 || 5 || T-6
+
T-6 || 8 || 5 || 117
 
|-
 
|-
| 8 || 6 || RHRS clock
+
RHRS clock || 8 || 6 || 118
 
|-
 
|-
| 8 || 7 || LHRS clock
+
LHRS clock || 8 || 7 || 119
 
|-
 
|-
| 8 || 8 || L1A_R
+
L1A_R || 8 || 8 || 120
 
|-
 
|-
| 8 || 9 || RHRS clock
+
RHRS clock || 8 || 9 || 121
 
|-
 
|-
| 8 || 10 || S2L
+
S2L || 8 || 10 || 122
 
|-
 
|-
| 8 || 11 || S2R
+
S2R || 8 || 11 || 123
 
|-
 
|-
| 8 || 12 || S0 or S2
+
S0 or S2 || 8 || 12 || 124
 
|-
 
|-
| 8 || 13 || ADC gate
+
ADC gate || 8 || 13 || 125
 
|-
 
|-
| 8 || 14 || RF Time
+
RF time || 8 || 14 || 126
 
|-
 
|-
| 8 || 15 || L1A
+
L1A || 8 || 15 || 127
 
|-
 
|-
| 8 || 16 || S2L-0
+
S2L-1 || 8 || 16 || 48
 
|-
 
|-
| : || : || :
+
| : || : || : ||
 
|-
 
|-
| 8 || 31 || S2L-16
+
S2L-16 || 8 || 31 || 63
 
|}
 
|}
  

Revision as of 10:02, 8 December 2017

Channel maps for F1TDCs and VETROC

Right HRS

Configuration valid starting from run 90465 (December 5, 2017):

T-1 || 8 || 0 || 112 T-2 || 8 || 1 || 113 T-3 || 8 || 2 || 114 T-4 || 8 || 3 || 115 T-5 || 8 || 4 || 116 T-6 || 8 || 5 || 117 RHRS clock || 8 || 6 || 118 LHRS clock || 8 || 7 || 119 L1A_R || 8 || 8 || 120 RHRS clock || 8 || 9 || 121 S2L || 8 || 10 || 122 S2R || 8 || 11 || 123 S0 or S2 || 8 || 12 || 124 ADC gate || 8 || 13 || 125 RF time || 8 || 14 || 126 L1A || 8 || 15 || 127 S2L-1 || 8 || 16 || 48 S2L-16 || 8 || 31 || 63
Signal F1 VME Slot F1 channel VETROC channel
: : :
F1 VME Slot F1 channel Signal
10 0 GC-01
: : :
10 9 GC-10
10 10 GC-SUM
10 11 S0A
10 12 S0B
10 13 S0coin
10 14 L1A
10 15 S2coin
10 16 S2R-1
: : :
10 31 S2R-16

Left HRS

Configuration valid starting from run 675 (December 5, 2017):

F1 VME Slot F1 channel Signal
14 0 S2L-1
: : :
14 15 S2L-16
14 16 CER-1
: : :
14 25 CER-10
14 26 GC SUM
14 27 S0A
14 28 S0B
14 29 S0coin
14 30 L1A
14 31 S2
F1 VME Slot F1 channel Signal
16 0 T1
16 1 T2
16 2 T3
16 3 (nothing)
16 4 S0 OR S2 RHRS
16 5 L1A_remote
16 6 clock RHS
16 7 clock LHRS
16 8 Shower Sum
16 9 S0 or S2 LHRS
16 10 S2 left
16 11 S2 right
16 12 S0 or S2 RHRS
16 13 all adc gate
16 14 L1A
16 15 RF signal
16 16 S2R-1
: : :
16 31 S2R-16