Difference between revisions of "Tritium DAQ page VME crate config"
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| Line 8: | Line 8: | ||
|'''Module''' ||CPU || Empty || TI || Empty || SD Board || FADC || FADC || FADC || FADC || FADC || Empty || F1 SD || Blank || F1 TDC || Blank || F1 TDC || Blank || MLU || ECL Splitter || Flex-IO || Blank | |'''Module''' ||CPU || Empty || TI || Empty || SD Board || FADC || FADC || FADC || FADC || FADC || Empty || F1 SD || Blank || F1 TDC || Blank || F1 TDC || Blank || MLU || ECL Splitter || Flex-IO || Blank | ||
|- | |- | ||
| − | |'''Module info''' || intelha3 - | + | |'''Module info''' || intelha3 - switched to halladaq8 in March || - || - || - || - || ACDI 762 || ACDI 786 || ACDI 201 || ACDI 420 || ACDI 809 || - || - || -|| - || - || -|| - ||1495 || -|| - || - |
|- | |- | ||
|'''Input Signals''' || - || - || - || - ||- || S2L || S2R || Cer&S0&Ref. || Raster || ? || || - || - || S2L&Cer&S0 || - || Trig & S2R || - || - || - || - || - | |'''Input Signals''' || - || - || - || - ||- || S2L || S2R || Cer&S0&Ref. || Raster || ? || || - || - || S2L&Cer&S0 || - || Trig & S2R || - || - || - || - || - | ||
|} | |} | ||
Revision as of 16:17, 31 August 2018
Left HRS
Configuration prior July 17 2018 (VME crate 31)
| slot # | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Module | CPU | Empty | TI | Empty | SD Board | FADC | FADC | FADC | FADC | FADC | Empty | F1 SD | Blank | F1 TDC | Blank | F1 TDC | Blank | MLU | ECL Splitter | Flex-IO | Blank |
| Module info | intelha3 - switched to halladaq8 in March | - | - | - | - | ACDI 762 | ACDI 786 | ACDI 201 | ACDI 420 | ACDI 809 | - | - | - | - | - | - | - | 1495 | - | - | - |
| Input Signals | - | - | - | - | - | S2L | S2R | Cer&S0&Ref. | Raster | ? | - | - | S2L&Cer&S0 | - | Trig & S2R | - | - | - | - | - |