Difference between revisions of "Tritium DAQ page VME crate config"

From Tritium Experiments Group
Jump to navigation Jump to search
Line 4: Line 4:
  
 
{| class="wikitable" style="text-align: center; width: 400px; height: 200px;"
 
{| class="wikitable" style="text-align: center; width: 400px; height: 200px;"
−
!slot #!!1!!2!!3!!4!!5!!6!!7!!8!!9!!10
+
!slot #!!1!!2!!3!!4!!5!!6!!7!!8!!9!!10!!11
 
|-
 
|-
−
|'''Module''' ||CPU ||- || -  || FADC || FADC || FADC || FADC || FADC || FADC || -  
+
|'''Module''' ||CPU ||- || - || -  || FADC || FADC || FADC || FADC || FADC || FADC || -  
 
|-
 
|-
−
|'''address ''' || -  || - || -  ||  0x280000|| 0x300000    ||0x380000    || 0x400000    ||0x480000    || 0x500000 || -  
+
|'''address ''' || -  || - || - || -  ||  0x280000|| 0x300000    ||0x380000    || 0x400000    ||0x480000    || 0x500000 || -  
 
|-  
 
|-  
−
|'''Input Signals''' || - || - || -    || Cer, S0 || S2L || S2R || BPM, Raster, PRL1-16,33, PRL2-16,33 || PRL1 0-15 || PLR1 17-32 || -
+
|'''Input Signals''' || - || -|| - || -    || Cer, S0 || S2L || S2R || BPM, Raster, PRL1-16,33, PRL2-16,33 || PRL1 0-15 || PLR1 17-32 || -
 
|-
 
|-
−
|'''Module info''' ||halladaq8 || - || - ||  ACDI-762  || ACDI-786  ||ACDI-201|| ACDI-420 || ACDI-809 || ACDI-407 || -
+
|'''Module info''' ||halladaq8 || - || - || - ||  ACDI-762  || ACDI-786  ||ACDI-201|| ACDI-420 || ACDI-809 || ACDI-407 || -
 
|}
 
|}
  
 
{|class="wikitable" style="text-align: center; width: 400px; height: 200px;"
 
{|class="wikitable" style="text-align: center; width: 400px; height: 200px;"
−
!slot #!!11!!12!!13!!14!!15!!16!!17!!18!!19
+
!slot #!!12!!13!!14!!15!!16!!17!!18!!19!!20!!21
 
|-
 
|-
 
|'''Module'''  || SD || FADC || FADC  || FADC || FADC || FADC || FADC || blank ||  MLU  || TI
 
|'''Module'''  || SD || FADC || FADC  || FADC || FADC || FADC || FADC || blank ||  MLU  || TI

Revision as of 16:42, 7 December 2018

Configuration After Tritium

Note: This is only here temporarily and should be copied to APEX wiki soon.

Left HRS (VXS crate 31)

slot # 1 2 3 4 5 6 7 8 9 10 11
Module CPU - - - FADC FADC FADC FADC FADC FADC -
address - - - - 0x280000 0x300000 0x380000 0x400000 0x480000 0x500000 -
Input Signals - - - - Cer, S0 S2L S2R BPM, Raster, PRL1-16,33, PRL2-16,33 PRL1 0-15 PLR1 17-32 -
Module info halladaq8 - - - ACDI-762 ACDI-786 ACDI-201 ACDI-420 ACDI-809 ACDI-407 -
slot # 12 13 14 15 16 17 18 19 20 21
Module SD FADC FADC FADC FADC FADC FADC blank MLU TI
address - 0x680000 0x700000 0x780000 0x800000 0x880000 0x900000 - - 0xA80000
Input Signals - PRL2 0-15 PRL2 17-32 SciFi (1) SciFi (2) SciFi (3) SciFi (4) - - -
Module info - ACDI-412 B21595-25R ACDI-811 ACDI-818 ACDI-821 ACDI-822 - v1495 -

Right HRS (VME crate 20)

slot # 1 2 3 4 5 6 7 8 9 10 11
Module CPU TI - MLU blank F1SD Blank F1 Blank F1 SD 8th Expansion
islot - - - - - - - - - - -
Input Signals - - - - - - - - - - -
Module info intelha3 - - v1495 - - - - - - -
slot # 12 13 14 15 16 17 18 19 20 21
Module FADC SD FADC FADC FADC FADC FADC FADC FADC FADC ECL FanOut
islot - 0 1 2 3 4 5 6 7 -
Input Signals - S2L S2R S0,GC SF(48-63) SF(0-15) SF(16-31) SF(32-47) BPM Raster -
Module info - ACDI-748 ACDI-783 ACDI-794 ACDI-823 ACDI-812 ACDI-814 ACDI-820 ACDI-817 -

Configuration from Aug 01 2018 till End of Tritium

Left HRS (VME crate 31)

slot # 1 2 3 4 5 6 7 8 9 10 11 12
Module CPU TI SD 8th Expansion SD Board FADC FADC FADC FADC FADC FADC FADC FADC
islot - - - - 0 1 2 3 4 5 6 7
Input Signals - - - - Cer, S0 S2L S2R BPM, Raster, PRL1-16,33, PRL2-16,33 PRL1 0-15 PLR1 17-32 PRL2 0-15 PRL2 17-32
Module info halladaq8 - - - ACDI-762 ACDI-786 ACDI-201 ACDI-420 ACDI-809 ACDI-407 ACDI-412 B21595-25R
slot # 13 14 15 16 17 18 19 20 21
Module Blank F1 SD Blank F1 TDC Blank F1 TDC Blank ECL FanOut MLU
Module info - - - - - - - - v1495
Input Signals - - - S2L&Cer&S0 - Trig & S2R - - -

Right HRS (VME crate 20)

slot # 1 2 3 4 5 6 7 8 9 10 11
Module CPU TI - MLU VETROC F1SD Blank F1 Blank F1 Blank
islot - - - - - - - - - - -
Input Signals - - - - - - - - - - -
Module info intelha3 - - v1495 - - - - - - -
slot # 12 13 14 15 16 17 18 19 20 21
Module FADC SD FADC FADC FADC FADC FADC FADC FADC - ECL FanOut
islot - 0 1 2 3 4 5 6 - -
Input Signals - S2L S2R S0,GC,A2 24-25 BPM Raster A2 A1/A2 A1 - -
Module info - ACDI-748 ACDI-783 ACDI-794 ACDI-817 ACDI-812 ACDI-814 ACDI-820 - -



Configuration prior July 17 2018

Left HRS (VME crate 31)

slot # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Module CPU Empty TI Empty SD Board FADC FADC FADC FADC FADC Empty F1 SD Blank F1 TDC Blank F1 TDC Blank MLU ECL FanOut Flex-IO Blank
Module info intelha3 - switched to halladaq8 in March - - - - ACDI 762 ACDI 786 ACDI 201 ACDI 420 ACDI 809 - - - - - - - 1495 - - -
Input Signals - - - - - S2L S2R Cer&S0&Ref. Raster ? - - S2L&Cer&S0 - Trig & S2R - - - - -
Retrieved from "https://wiki.jlab.org/tegwiki/index.php?title=Tritium_DAQ_page_VME_crate_config&oldid=3386"