EJFAT Group Meeting May 02, 2024

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The meeting time is 11:00am Eastern/USA.

Connection Info:

You can connect using [ https://jlab-org.zoomgov.com/j/1611828967?pwd=UVVCS0pUVW5FMlphT0lRQXdoQ0o4Zz09&from=addon ZoomGov Video conferencing (ID: 161 012 5238)]. (Click "Expand" to the right for details -->): 

Meeting URL
 https://jlab-org.zoomgov.com/j/1611828967

Meeting ID
161 182 8967

Passcode
570041

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Dial one of the following numbers:
US: +1 669 254 5252 or +1 646 828 7666 or +1 551 285 1373 or +1 669 216 1590 or 833 568 8864 (Toll Free)

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Agenda:

  1. Previous meeting
  2. Announcements:
    1. 24th Real Time Conference – ICISE, Quy Nhon, Vietnam 22-26 April 2024 - Presentation
    2. EJFAT API
  3. System Status:
  4. NERSC Test Development:
    1. Data Source:
      1. JLAB, CLAS12, pre-triggered events - 1 channel
    2. Data Sink:
      1. Perlmutter
      2. ERSAP
    3. Test Plans - JLab, ESnet, NERSC:
    4. 100 Gbps / 38 Node Test
  5. ORNL/ESnet/JLab IRI Testbed (similar to NERSC) - Ross Miller <rgmiller@ornl.gov> project code CSC 266
    1. Waiting on ORNL Internal Network Security
  6. ALS
    1. Socializing Experiment Agenda - In Review
    2. Hoping for First Runs Summer 2024
  7. JLab FEG/SRO - need long term solution for event sync
  8. EJFAT Reconfig meetings/Tools to explore options
    1. Exploring Linux commands/utilities and system bios settings for automated probing of configuration
    2. Rec'd 22 PCIe VPI NICS
    3. Rec'd 5 OCP3/SFF VPI NICS
    4. Surrendering indra-s2; moving U280 to ejfat-3
  9. EJFAT Phase II
    1. Implementation details in the DAOS gateway.
      1. Need to spec DAOS Use Cases ?
      2. Intel standing up special slack channel to discuss DAOS
      3. Connection Strategy to DAOS
      4. Specially when to keep track of how the FPGA would DMA event data cells in the future if it was a SmartNIC card. ( Cissie )
      5. daosfs01​ has 2 physical IB cards and can run 2 true engines with each CPU socket hosting one engine.
    2. Progress of multi FPGA and multi virtual LB control plane sw. ( Derek )
    3. Progress of FPGA architecture ( Peter and Jonathan )
      1. LB FW currently limited to 100 Gbps
      2. Reassembly work commencing soon
    4. Progress of finalizing a reassembly frame format (subordinate to 4.) ( Carl / Stacey )
    5. Progress on software development for NVIDIA Bluefield2 DPU data steering from NIC to GPU memory ( Amitoj/Cissie )
  10. Resources:
    1. HPDF
  11. AOT
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