EJFAT Group Meeting May 30, 2024

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The meeting time is 11:00am Eastern/USA.

Connection Info:

You can connect using [ https://jlab-org.zoomgov.com/j/1611828967?pwd=UVVCS0pUVW5FMlphT0lRQXdoQ0o4Zz09&from=addon ZoomGov Video conferencing (ID: 161 012 5238)]. (Click "Expand" to the right for details -->): 

Meeting URL
 https://jlab-org.zoomgov.com/j/1611828967

Meeting ID
161 182 8967

Passcode
570041

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Dial one of the following numbers:
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Agenda:

  1. Previous meeting
  2. Announcements:
  3. System Status:
  4. NERSC Test Development:
    1. Data Source:
      1. JLAB, CLAS12, pre-triggered events - 1 channel
    2. Data Sink:
      1. Perlmutter
      2. ERSAP
    3. Test Plans - JLab, ESnet, NERSC:
    4. 100 Gbps / 25 - 40 Node Test
  5. ORNL/ESnet/JLab IRI Testbed (similar to NERSC) - Ross Miller <rgmiller@ornl.gov> project code CSC 266
    1. Waiting on ORNL Internal Network Security
  6. ALS
    1. Socializing Experiment Agenda - In Review
    2. Hoping for First Runs Summer 2024
  7. JLab FEG/SRO - will use interim UDP solution for event sync - heats up in June
  8. Installing LBs on ejfat-1,2,3,4,5,6,fs
    1. Updated installation procedure
    2. ejfat-6 complete / tested
    3. ejfat-5 complete but only lightly tested
    4. ejfat-fs almost complete - waiting resolution on SSD /nvme
  9. EJFAT Phase II
    1. Need long term solution for CP/Source event sync
    2. Implementation details in the DAOS gateway.
      1. Need to spec DAOS Use Cases ?
      2. Intel standing up special slack channel to discuss DAOS
      3. Connection Strategy to DAOS
      4. Specially when to keep track of how the FPGA would DMA event data cells in the future if it was a SmartNIC card. ( Cissie )
      5. daosfs01​ has 2 physical IB cards and can run 2 true engines with each CPU socket hosting one engine.
    3. CP capable of multi FPGA and multi virtual DP
    4. Progress of FPGA architecture ( Peter and Jonathan )
      1. LB FW currently limited to 100 Gbps
      2. Reassembly work commencing soon
    5. Progress of finalizing a reassembly frame format (subordinate to 4.) ( Carl / Stacey )
    6. Progress on software development for NVIDIA Bluefield2 DPU data steering from NIC to GPU memory ( Amitoj/Cissie )
  10. Resources:
    1. HPDF
    2. EJFAT API
  11. AOT
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