Difference between revisions of "EJFAT"

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<div id="header">
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<div class="orbitron"><font size="+3">Welcome to the EJFAT Wiki</font><br></div>('''E'''Snet / '''J'''LaB '''F'''PGA '''A'''ccelerated '''T'''ransport)
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<h1 class="title">EJFAT</h1>
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<h3 class="date">June, 2021</h3>
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<br><hr><br>
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</div>
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<div class="orbitron"><font size="+1">System Overview:</font></div>''EJFAT is a collaboration between Energy Sciences Network (ESnet) and Thomas Jefferson National Laboratory (JLab) for proof of concept engineering to program a Field Programmable Gate Array (FPGA) for network data routing of commonly tagged UDP packets from any data source to individual and configurable destination endpoints in an end-point compute work load balanced manner, including some additional tagging for stream reassembly at the endpoint. The primary purpose of this FPGA based acceleration is to load balance work to destination compute farm endpoints with low latency and full line rate bandwidth of 100 Gbs with feedback from the destination compute farm.
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<p>We describe a collaboration between Energy Sciences Network (ESnet) and Thomas Jefferson National Laboratory (JLab) for proof of concept engineering to construct a ''dedicated'' data transport network that delivers streamed (non-triggered) data from the JLab Data Acquisition System (DAQ) to a back-end compute farm using an intervening Field Programmable Gate Array (FPGA) to time-stamp aggregate across DAQ channels and load balance work to individual compute farm destinations in a farm status aware manner.</p>
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<p>We describe a collaboration between Energy Sciences Network (ESnet) and Thomas Jefferson National Laboratory (JLab) for proof of concept engineering to program a Field Programmable Gate Array (FPGA) for network data transport acceleration via aggregation of designated UDP data packets for routing to individual and configurable destination endpoints including some options for stream reassembly at the endpoint by other devices.</p>
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== EJFAT System Status ==
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<p>We describe a collaboration between Energy Sciences Network (ESnet) and Thomas Jefferson National Laboratory (JLab) for proof of concept engineering to program a Field Programmable Gate Array (FPGA) for network data routing of commonly tagged UDP packets to individual and configurable destination endpoints in a follow-on compute work load balanced manner, including some additional tagging for stream reassembly at the endpoint. The primary purpose of this FPGA based acceleration is to load balance work to destination compute farm endpoints with low latency and full line rate bandwidth of 100 Gbs with feedback (back-pressure) from the destination compute farm. ESnet used P4 programming on the FPGA to use meta-data in the UDP packet stream to route packets with a common tag to dynamically configurable endpoints controlled by the endpoint farm. Control plane programming tasks included back-pressure notifications from destination endpoints and notification processing by the FPGA host CPU to dynamically re-configure routing tables for the FPGA P4 code. <span><em>WHAT we found</em></span> (TBD)<br /><span><em>WHAT it means</em></span> (TBD)<br /></p>
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=== ejfat-1 ===
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<h1 id="ejfat-overview">EJFAT Overview</h1>
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# 200Gbps NIC: ejfat-1-daq  129.57.177.8
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<h4 id="section"></h4>
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# 10Gbps NIC:  ejfat-1      129.57.177.131
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<p>This collaboration between ESnet and JLab for FPGA Accelerated Transport (EJFAT) seeks a network data transport capability to aggregate and dynamically route selected UDP traffic with endpoint feedback.<br /></p>
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# U280 FPGA:  ejfat-1-dp    129.57.177.11
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<p>EJFAT will add meta-data to UDP data streams to be used both by the intervening FPGA, acting as a work Load Balancer (LB), to aggregate data packets from multiple logical input streams and dynamically route to endpoints and for an endpoint Reassembly Engine (RE) to perform custom reassembly resulting from network equipment fragmentation.<br /></p>
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# Test moving a current LB install wholesale by moving files/containers
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<p>While the aggregation and routing meta-data included as the header in the payload is generic in design, it is being first utilized for streamed (non-triggered) data from the JLab DAQ to the back-end compute farm.<br /></p>
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# IT Account Setup Sandbox
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<p>In the initial JLab deployment context, the FPGA will time-stamp aggregate across detector Data Acquisition System (DAQ) channels for the purpose of load balancing work to individual compute farm destinations in a farm status aware manner (see Figure [fig:ejfat] in Appendix [appendix:ejfat]), where <span><em>work</em></span> here is concerned with using data from an individual time-stamp across all DAQ channels to identify or reconstruct detector <span><em>events</em></span>.<br /></p>
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<p>This load balancing of computational work is under direct control of the compute farm via dynamic management of routing information communicated to the FPGA host CPU which is passed on to the FPGA.<br /></p>
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=== ejfat-2 ===
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<p>As the aggregated/routed data is opaque to this design, it should be reusable for other data streams with aggregation/routing needs.</p>
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# 200Gbps NIC: ejfat-2-daq  129.57.177.2
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<h1 id="sec:roc">Read Out Controller Processing</h1>
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# 10Gbps NIC:  ejfat-2      129.57.177.132
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<p>The Read Out Controllers (ROC) of the JLab DAQ system will be enhanced to stream data via UDP and include new meta-data prepended to the original payload that serves the needs of the compute destination LB and the destination fragmentation RE. Figure [fig:roc] is a diagram of the new data stream processing requirements for the JLaB DAQ system.<br /></p>
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# U280 FPGA:  ejfat-2-dp    129.57.177.12
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<p>This new meta-data, populated by the JLab DAQ system, consists of two parts, the first for the LB and the second for the RE.</p>
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# LB: DP latest prod FW, CP Main branch Jan 4 Rev, CP/FW upgrades pending
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<h2 id="sec:Load Balancer Meta-Data">Load Balancer Meta-Data</h2>
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# IOMMU enabled
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<p>The LB meta-data (Figure [fig:roc], cyan section) is 96 bits that in order consists of</p>
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=== ejfat-3 ===
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<ul>
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# 200Gbps NIC: ejfat-3-daq  129.57.177.3
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<li><p>is 32 bits (bits 0-31) such that</p>
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# 10Gbps NIC:  ejfat-3      129.57.177.133
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<ul>
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# U280 FPGA:  ejfat-3-dp    129.57.177.13
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<li><p>bits 0-7 ASCII character ’L’</p></li>
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# Ready to accept second FPGA - needs addition PCIe riser
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<li><p>bits 8-15 ASCII character ’B’</p></li>
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=== ejfat-4 ===
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<li><p>bits 16-23 LB version number starting at 1 (constant for run duration)</p></li>
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# 200Gbps NIC: ejfat-4-daq  129.57.177.4
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<li><p>bits 24-31 Protocol Number (very useful for protocol decoders e.g., wireshark/tshark )</p></li>
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# 10Gbps NIC:  ejfat-4      129.57.177.134
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</ul></li>
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# U280 FPGA:  ejfat-4-dp    129.57.177.14
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<li><p>(Time stamp or proxy) is a 64 bit quantity (bits 32-95) that for a DAQ run duration</p>
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# XDP experiments
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<ul>
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=== ejfat-5 ===
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<li><p>Monotonically increases</p></li>
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# 200Gbps NIC: ejfat-5-daq  129.57.177.5
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<li><p>Unique</p></li>
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# 10Gbps NIC:  ejfat-5      129.57.177.135
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<li><p>Never rolls over</p></li>
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# U280 FPGA:  ejfat-5-dp    129.57.177.15
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<li><p>Never resets</p></li>
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# LB: DP latest prod FW, CP Dev branch April 11 Rev (Latest)
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<li><p>Serves as a common tag across multiple DAQ ROC channels/packets related to the same time-stamped data transfer.</p></li>
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</ul></li>
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=== ejfat-6 ===
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</ul>
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# 200Gbps NIC: ejfat-6-daq  129.57.177.6
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<h4 id="section-1"></h4>
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# 10Gbps NIC: ejfat-6      129.57.177.136
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<p>In standard IETF RFC format:<br /></p>
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# U280 FPGA:  ejfat-6-dp    129.57.177.16
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<pre><code>protocol &#39;L:8,B:8,Version:8,Protocol:8,Tick:64&#39;
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# DAOS experiments
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0                  1                   2                  3 
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# IOMMU enabled
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0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
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=== ejfat-fs ===
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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# 200Gbps NIC: ejfat-fs-daq  129.57.177.7
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|       L      |       B      |   Version    |    Protocol  |
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# 10Gbps NIC:  ejfat-fs      129.57.177.130
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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# U280 FPGA:  ejfat-fs-dp    129.57.177.10
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|                                                               |
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# Hosts NVME memory/disk
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+                              Tick                            +
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|                                                               |
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== Presentations/Papers ==
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</code></pre>
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{| class="wikitable"
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<h2 id="sec:Reassembly Engine Meta-Data">Reassembly Engine Meta-Data</h2>
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|-
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<p>The RE meta-data (Figure [fig:roc], yellow section) is 64 bits and consists of</p>
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!date
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<ul>
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!presenter
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<li><p>bits 0-3 Version number</p></li>
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!Event
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<li><p>bits 4-13 Reserved</p></li>
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!links
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<li><p>bit 14 indicates first packet</p></li>
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|-
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<li><p>bit 15 indicates last packet</p></li>
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|2021-03-01
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<li><p>bits 16-31 ROC Id</p></li>
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|G. Heyes
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<li><p>bits 32-63 packet sequence number or optionally data offset byte number for reassembly</p></li>
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|EJFAT Proposal
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</ul>
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|[https://jeffersonlab.sharepoint.com/:w:/r/sites/SciComp/_layouts/15/Doc.aspx?sourcedoc=%7B65DA331C-40E4-4761-B643-251BFA309C45%7D&file=20210525%20ASCR%20BRN%20Solicitation%20v4.docx&action=default&mobileredirect=true Word]
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<h4 id="section-2"></h4>
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|-
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<p>In standard IETF RFC format:<br /></p>
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|2021-10-21
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<pre><code>protocol &#39;Version:4,Rsvd:10,First:1,Last:1,ROC-ID:16,Offset:32&#39;
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|M. S. Goodrich
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0                  1                  2                  3 
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|Div Brief
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0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
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|[https://jeffersonlab.sharepoint.com/sites/SciComp/Shared%20Documents/EPSCI/EJFAT/EJFAT_for_Div.pdf?CT=1638970015731&OR=ItemsView PDF]
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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|-
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|Version|        Rsvd      |F|L|            ROC-ID            |
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|2021-11-05
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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|M. S. Goodrich
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|                            Offset                            |
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|Canisius College
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+</code></pre>
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|[https://jeffersonlab.sharepoint.com/sites/SciComp/Shared%20Documents/EPSCI/EJFAT/canisius.pdf?CT=1638970328329&OR=ItemsView PDF]
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<h4 id="section-3"></h4>
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|-
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<p>The resultant DAQ data stream is shown just below the block diagram in Figure [fig:roc] and depicts the stream UDP packet structure from the DAQ system to the LB. Individual packets are meta-data tagged both for the LB, to route based on <span><em>tick</em></span> to the proper compute node, and for the RE with packet <span><em>offset</em></span> spanning the collection of packets for a single <span><em>tick</em></span> for eventual destination reassembly.<br /></p>
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|2021-12-03
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<p>The depicted sequence is only illustrative, and no assumption about the order of packets with respect to either <span><em>tick</em></span> or <span><em>offset</em></span> should be made by the LB or the RE.</p>
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|S. Sheldon
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<div class="figure">
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|ESnet LB Tutorial
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<img src="esnet-jlab-network-diagram-v002d-roc.png" alt="[fig:roc]ROC Data Stream Processing " /><p class="caption">[fig:roc]ROC Data Stream Processing </p>
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|[https://jeffersonlab.sharepoint.com/:v:/r/sites/SciComp/Shared%20Documents/EPSCI/EJFAT/ESnet_EJFAT_Tut.mp4?csf=1&web=1&e=4nDeZ2 MP4]
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</div>
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|-
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<h2 id="sec:UDP Header">UDP Header</h2>
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|2021-12-10
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<p>The UDP Header will be populated as follows:</p>
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|Y. Kumar
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<ul>
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|SRO iX Presentation
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<li><p>: lower 16 bits of Load Balancer <span><em>Tick</em></span> (for LAG switch entropy)</p></li>
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|[https://jeffersonlab.sharepoint.com/:p:/r/sites/SciComp/Shared%20Documents/EPSCI/EJFAT/EJFAT_SRO_iX.pptx?d=w78e41e5ddab04d21a4c26f93ac84b7d6&csf=1&web=1&e=gkaCDS PPTX]
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<li><p>: Value that indicates LB should perform load balancing (else packet is discarded)</p></li>
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|-
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</ul>
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|2022-08-05
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<p>The resultant DAQ data stream is shown below the block diagram and depicts the stream UDP packet structure. Individual packets</p>
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|M. S. Goodrich
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<h2 id="sec:rocag">ROC Aggregation Switch</h2>
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|RT-2022 Presentation
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<p>Individual ROC channels will be aggregated for maximum throughput by a switch using Link Aggregation Protocol (LAG) or similar where the network traffic downstream of the switch will be addressed to the LB FPGA (see (Figure [fig:ejfat], Appendix [appendix:ejfat]).<br /></p>
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|[https://jeffersonlab.sharepoint.com/:p:/r/sites/SciComp/Shared%20Documents/EPSCI/EJFAT/JLab%20EJFAT-msg.pptx?d=w7a8e53d19a584fefb1405fa8ff190b1e&csf=1&web=1&e=50bX4g PPTX]
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<p>If the LAG configured switch proves to be incapable of meeting line rate throughput (100Gbs), then an additional FPGA(s) can be engineered to subsume this function as depicted in Figure [fig:roc<sub>l</sub>ag].</p>
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|-
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[[File:Esnet-JLab-network-diagram-v002a-roc-1.png|border|"caption"]]
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|2022-08-05
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<h1 id="sec:lb">LB Processing</h1>
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|M. S. Goodrich, et al.
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<p>The FPGA resident LB aggregates data across all DAQ channels for a single discrete <span><em>tick</em></span> and routes this aggregated data to individual end compute nodes in cooperation with the FPGA host chassis CPU using algorithms designed for the host CPU and feedback received from the end compute node farm, maintaining complete opacity of the UDP payload to the LB (except for the LB meta-data).</p>
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|RT-2022 Proceedings
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<h2 id="sec:data-pln">Data Plane (FPGA) Processing</h2>
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|[https://jeffersonlab.sharepoint.com/:b:/r/sites/SciComp/Shared%20Documents/EPSCI/EJFAT/EJFAT_rt2022.pdf?csf=1&web=1&e=NFHXHM PDF]
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<div class="figure">
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|-
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<img src="LB-data-pln.png" alt="[fig:dpfc]Data Plane Flow Chart" /><p class="caption">[fig:dpfc]Data Plane Flow Chart</p>
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|2022-10-20
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</div>
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|S. Sheldon, et al.
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<ul>
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|INDIS-2022
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<li><p>Packet Parsing Stage</p>
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|[https://jeffersonlab.sharepoint.com/:b:/r/sites/SciComp/Shared%20Documents/EPSCI/EJFAT/Indis_Paper_2022-3.pdf?csf=1&web=1&e=tmhpfA PDF]
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<ul>
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|-
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<li><p>Headers defined in the previous stage will be parsed and made available for the remaining stages.</p></li>
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|2022-10-24
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<li><p>The Event Payload MUST NOT be parsed by the load balancer.</p></li>
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|M. S. Goodrich
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</ul></li>
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|ACAT-2022 Presentation
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<li><p>Input Packet Filter Stage</p>
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|[https://jeffersonlab.sharepoint.com/:p:/r/sites/SciComp/Shared%20Documents/EPSCI/EJFAT/EJFAT-acat2022.pptx?d=wc024332f3cf7440eae15e4f6f3646897&csf=1&web=1&e=QEwIcx PPTX]
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<ul>
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|-
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<li><p>Implemented as a P4 table with the following properties</p></li>
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|2023-03-17
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<li><p>Max Entries: 32</p></li>
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|M. S. Goodrich, et al.
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<li><p>Key:</p>
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|ACAT-2022 Proceedings
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<ul>
+
|[https://jeffersonlab.sharepoint.com/:b:/r/sites/SciComp/Shared%20Documents/EPSCI/EJFAT/EJFAT_ACAT_2022_QL_sub.pdf?csf=1&web=1&e=dR566P PDF]
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<li><p>(Exact Match) EtherType</p></li>
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|-
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<li><p>(Exact Match) (96b 0 <span class="math"> ∥ </span> IPv4 Dst) OR IPv6 Dst</p></li>
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|2023-05-11
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<li><p>(Binary Match) UDP Dst Port</p></li>
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|M. S. Goodrich, et al.
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</ul></li>
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|CHEP-2023 Presentation
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<li><p>Value: None</p></li>
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|[https://jeffersonlab.sharepoint.com/:p:/r/sites/SciComp/Shared%20Documents/EPSCI/EJFAT/EJFAT-chep2023.pptx?d=w605623a55051446e9d2bcca80f64eda6&csf=1&web=1&e=NHSloC PPTX]
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<li><p>A miss in this table MUST result in the packet being discarded since it is not intended for the load balancer.</p></li>
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|-
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<li><p>The P4 code in this stage must also check both the Magic and Version fields in the LB Header. A mismatch from the expected values MUST result in the packet being discarded.</p></li>
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|2023-10-12
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</ul></li>
+
|D. Howard, et al.
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<li><p>Calendar Epoch Assignment Stage</p>
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|CHEP-2023 Conference Publication
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<ul>
+
|[https://jeffersonlab.sharepoint.com/:b:/r/sites/SciComp/Shared%20Documents/EPSCI/EJFAT/chep2023_proceedings.pdf?csf=1&web=1&e=FO7f8j PDF]
−
<li><p>Implemented as a P4 table with the following properties</p></li>
+
|-
−
<li><p>Max Entries: 128</p></li>
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|2024-03-11
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<li><p>Key: (Ternary Match) 64b LB Event Number (Timestamp)</p></li>
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|M. S. Goodrich, et al.
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<li><p>Value: 32b Calendar Epoch</p></li>
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|ACAT-2024 Presentation
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</ul></li>
+
|[https://jeffersonlab.sharepoint.com/:p:/r/sites/SciComp/Shared%20Documents/EPSCI/EJFAT/Acat2024.pptx?d=wb4c9cc47a8eb4b299c3dab1aaa379a36&csf=1&web=1&e=Kct82Y} PPTX]
−
<li><p>Load Balance Calendar to Member Map Stage</p>
+
|-
−
<ul>
+
|2024-04-10
−
<li><p>Implemented as a P4 table with the following properties</p></li>
+
|M. S. Goodrich, et al.
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<li><p>Max Entries: 2048</p></li>
+
|RT-2024 Presentation
−
<li><p>Key:</p>
+
|[https://jeffersonlab.sharepoint.com/:p:/r/sites/SciComp/Shared%20Documents/EPSCI/EJFAT/rt2024.pptx?d=w0dba99dbb67f481f9a39907dbec384b8&csf=1&web=1&e=1XISCm} PPTX]
−
<ul>
+
|}
−
<li><p>(Exact Match) 32b Calendar Epoch</p></li>
+
 
−
<li><p>(Exact Match) 9b Calendar Slot (ie. LB Event Number &amp; 0x1FF)</p></li>
+
== EJFAT Weekly EPSCI Meetings ==
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</ul></li>
+
 
−
<li><p>Value: 16b LB Member ID</p></li>
+
[[EJFAT Weekly EPSCI Meetings]]
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</ul></li>
+
 
−
<li><p>Load Balance Member Info Lookup Stage</p>
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== EJFAT Weekly Collaboration Meetings ==
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<ul>
+
 
−
<li><p>Implemented as a P4 table with the following properties</p></li>
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[[EJFAT Weekly Meetings]]
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<li><p>Max Entries: 1K</p></li>
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<li><p>Key:</p>
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== Technical Design Overview ==
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<ul>
+
 
−
<li><p>(Exact Match) 16b EtherType (IPv4 or IPv6)</p></li>
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[[EJFAT Technical Design Overview]]
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<li><p>(Exact Match) 16b LB Member ID</p></li>
+
 
−
</ul></li>
+
[[UDP Packet Header Formats]]
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<li><p>Value:</p>
+
 
−
<ul>
+
[https://jeffersonlab.sharepoint.com/:p:/r/sites/HPDF/_layouts/15/Doc.aspx?sourcedoc=%7BEABA533A-E516-4C57-BE85-BBF594F5E918%7D&file=Jan%2010%20HPDF%20Conceptual%20Machine%20Design%20Concept.pptx&action=edit&mobileredirect=true IRIAD/EJFAT Testbed]
−
<li><p>8b Action ID</p>
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−
<ul>
+
== UDP Transmission Performance ==
−
<li><p>1 = IPv4 Rewrite</p></li>
+
 
−
<li><p>2 = IPv6 Rewrite</p></li>
+
[[EJFAT UDP General Information]]
−
</ul></li>
+
 
−
<li><p>IPv4 Rewrite Action</p>
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[[EJFAT UDP General Performance Considerations]]
−
<ul>
+
 
−
<li><p>48b MAC DA (for next-hop router)</p></li>
+
[[EJFAT UDP Packet Receiving and Core Switching]]
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<li><p>32b IPv4 Dst</p></li>
+
 
−
<li><p>16b UDP Dst Port</p></li>
+
[[EJFAT UDP Packet Sending and NUMA Nodes]]
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</ul></li>
+
 
−
<li><p>IPv6 Rewrite Action</p>
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[[EJFAT UDP Single Thread Packet Sending and Receiving]]
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<ul>
+
 
−
<li><p>48b MAC DA (for next-hop router)</p></li>
+
[[Testing Load Balancer Bandwidth]]
−
<li><p>128b IPv6 Dst</p></li>
+
 
−
<li><p>16b UDP Dst Port</p></li>
+
== HOW-TOs ==
−
</ul></li>
+
 
−
</ul></li>
+
[[How to setup ejfat nodes]]
−
<li><p>Rewrite Action type must match the input packet’s EtherType. E.g. An Input IPv4 packet cannot use the IPv6 Rewrite Action and vice versa.</p></li>
+
 
−
<li><p>Before applying the rewrite actions, the original packet’s MAC DA should be copied into the MAC SA. This will ensure that the outgoing packet will be sent from exactly the MAC address that the original packet was destined to. This will help to keep the MAC FDB entries in the adjacent switches from expiring.</p></li>
+
[[How to install, build and use gRPC]]
−
<li><p>Packets will be transmitted back out the port they were received on.</p></li>
+
 
−
</ul></li>
+
[[How to install, build and use XDP related packages]]
−
</ul>
+
 
−
<h4 id="section-4"></h4>
+
[https://jeffersonlab.sharepoint.com/:b:/r/sites/SciComp/Shared%20Documents/EPSCI/EJFAT/CP_PID_Sched.pdf?csf=1&web=1&e=JpffJ4 How to Compute Schedule Density from PID Signals]
−
<p>The resultant LB data stream is shown just above the block diagram in Figure [fig:lb] and depicts the stream UDP packet structure from the LB to the RE concerning an arbitrary <span><em>single</em></span> destination compute node. Individual packets here are still meta-data tagged both for the LB and RE. <strong>The RE for a target compute node will see a collection of packets that share a common <span><em>tick</em></span></strong>.<br /></p>
+
 
−
<p>The depicted sequence is only illustrative, and no assumption about the order of packets with respect to the <span><em>offset</em></span> should be made by the RE.<br /></p>
+
[https://jeffersonlab.sharepoint.com/:b:/r/sites/SciComp/Shared%20Documents/EPSCI/EJFAT/E2SAR.drawio.pdf?csf=1&web=1&e=E0Uqlh EJFAT API]
−
<h2 id="sec:cntrl-pln">Control Plane (Host CPU) Processing</h2>
+
 
−
<div class="figure">
+
== Edge to Core Test Equipment: ==
−
<img src="LB-cntrl-pln.png" alt="[fig:cpfc]Control Plane Flow Chart" /><p class="caption">[fig:cpfc]Control Plane Flow Chart</p>
+
 
−
</div>
+
# [https://jeffersonlab.sharepoint.com/:x:/r/sites/SciComp/Shared%20Documents/EPSCI/EJFAT/Edge-to-Core-Test-Stand-12102021.xlsx?d=w8de06c441cd442fd8d3f1b7d7983028d&csf=1&web=1&e=wKS9Lh Price Estimate Spreadsheet]
−
<ul>
+
# [https://jeffersonlab.sharepoint.com/:b:/r/sites/SciComp/Shared%20Documents/EPSCI/EJFAT/EJFAT-Test-Stand-Network-Map.pdf?csf=1&web=1&e=iWvvet Networking Diagram], [[Media:20240209_EJFAT_diagram.pdf | Updated (PDF)]] (from Brent 2024-02-09)
−
<li><p>Software Initialization Steps</p>
+
# [https://misportal.jlab.org/reqs/pr/viewPr.do?prNum=408549 PR408549] : Requisition 1 of 2 :
−
<ul>
+
## [https://jeffersonlab.sharepoint.com/:w:/r/sites/SciComp/Shared%20Documents/EPSCI/EJFAT/EJFAT-Test-Stand-Servers-SOW.docx?d=w19107d52332948a0b2924b13939c3f64&csf=1&web=1&e=CS6Ub8 Statement of Work for Servers]
−
<li><p>PROPOSAL: A low-level C Software library will be provided to allow insertion/deletion of table entries into each of the P4 tables. All other SW will likely need to be written by the user of the LB pipeline.</p></li>
+
## 1/13/2022: EJFAT team decided to solicit two bid responses, one with MLX NIC and one without. Response from Procurement is "I can ask for the two separate quotes.  If you are going to purchase both option (with & without add-in cards), once I receive the quotes back, you will have submit a new PR to cover the option (without add-in cards)."
−
<li><p>Populate Input Packet Filter Table</p>
+
## 1/18/2022: Question from KOI Computers: "please clarify what the part number for the NVIDIA Dual Port ConnectX-6". Replied with part # MCX623106AN-CDAT.
−
<ul>
+
## 1/24/2022: Requisition currently open for bid responses from vendors. Due date is COB 1/24/2022.
−
<li><p>Table Insert <span class="math">⟨</span>0x800, LB IPv4 Addr, LB UDP Dst<span class="math">⟩</span></p></li>
+
## 1/27/2022: PO awarded to Atipa for 6 servers and 1 file-server with FPGA and MLX SmartNIC. Expected delivery date from vendor is 5/31/2022.
−
<li><p>Table Insert <span class="math">⟨</span>0x86dd, LB IPv6 Addr, LB UDP Dst<span class="math">⟩</span></p></li>
+
# [https://misportal.jlab.org/reqs/pr/viewPr.do?prNum=408870 PR408870] [https://misportal.jlab.org/reqs/pr/viewPr.do?prNum=408938 PR408938] Requisition 2 of 2: Statement of Work for Switches & Cables
−
</ul></li>
+
## 1/14/2022: PRs for the switches, transceivers and fiber have been submitted. I added (4) 2km 100G transceivers to support dual 100G connections between the switches.  We can always upgrade to 400G in the future, if needed.
−
<li><p>Populate Load Balance Member Table: For each LB Member</p>
+
# [https://misportal.jlab.org/reqs/pr/viewPr.do?prNum=409850 PR409850] [https://developer.nvidia.com/arm-hpc-devkit NVIDIA ARM HPC Developer Kit]
−
<ul>
+
## Hardware Specifications for dev kit
−
<li><p>Allocate next free Member ID number from SW pool</p></li>
+
##: [[Model]] GIGABYTE G242-P32, 2U server
−
<li><p>Table Insert</p>
+
##: [[CPU]] 1x Ampere Altra Q80-30 (Arm processor)
−
<ul>
+
##: [[Memory]] 512G DDR4 memory
−
<li><p>K: <span class="math">⟨</span>0x800, Member ID<span class="math">⟩</span></p></li>
+
##: [[Storage]] 6TB SAS/ SATA 3.5″
−
<li><p>V: <span class="math">⟨</span>IPv4 Rewrite, 0, Next-Hop MAC DA, Worker IPv4 Dst, Worker UDP Dst Port<span class="math">⟩</span></p></li>
+
##: [[GPU]] 2x NVIDIA A100 GPU
−
</ul></li>
+
##: [[Network]] 2x NVIDIA® BlueField®-2 E-Series DPU, 200GbE/HDR single-port QSFP56, PCIe Gen4 x16, secure boot enabled, crypto disabled, 16GB on-board DDR, 1GbE OOB management
−
<li><p>Table Insert</p>
+
 
−
<ul>
+
== Resources ==
−
<li><p>K: <span class="math">⟨</span>0x86dd, Member ID<span class="math">⟩</span></p></li>
+
* [https://jeffersonlab.sharepoint.com/:b:/r/sites/SciComp/Shared%20Documents/EPSCI/EJFAT/u280_po_Signed_21-M0862%20-%20Avnet.pdf?csf=1&web=1&e=PmJfdu First FPGA PO]
−
<li><p>V: <span class="math">⟨</span>IPv6 Rewrite, 0, Next-Hop MAC DA, Worker IPv6 Dst, Worker UDP Dst Port<span class="math">⟩</span></p></li>
+
* [https://www.jlab.org TBD]
−
</ul></li>
 
−
</ul></li>
 
−
<li><p>Populate Load Balance to Member Map Table</p>
 
−
<ul>
 
−
<li><p>Allocate next free Calendar Epoch number from SW pool</p></li>
 
−
<li><p>Assign all active LB Member IDs to the 512 Calendar Slots</p>
 
−
<ul>
 
−
<li><p>Any members can occur between 0-512 times in the calendar</p></li>
 
−
<li><p>A member occurring more times in the calendar has a higher “weight” and will be more likely to be assigned an event within this Calendar Epoch</p></li>
 
−
<li><p>All 512 slots MUST have a member assigned to them or events that target the empty slot will be entirely discarded by the load balancer</p></li>
 
−
</ul></li>
 
−
<li><p>For each Calendar Slot Table Insert</p>
 
−
<ul>
 
−
<li><p>K: <span class="math">⟨</span>Calendar Epoch, Calendar Slot<span class="math">⟩</span></p></li>
 
−
<li><p>V: <span class="math">⟨</span>LB Member ID<span class="math">⟩</span></p></li>
 
−
</ul></li>
 
−
</ul></li>
 
−
<li><p>Populate the Calendar Epoch Assignment Table</p>
 
−
<ul>
 
−
<li><p>Assign all Event IDs (Timestamps) to the newly allocated Calendar Epoch</p></li>
 
−
<li><p>Table Insert</p>
 
−
<ul>
 
−
<li><p>K: <span class="math">⟨</span>*<span class="math">⟩</span></p></li>
 
−
<li><p>V: <span class="math">⟨</span>Calendar Epoch<span class="math">⟩</span></p></li>
 
−
</ul></li>
 
−
</ul></li>
 
−
<li><p>The load balancer will now assign each Rx’d packet to exactly one of the LB members based on the Event ID contained in the packet. The mapping will remain consistent for any given Event ID within an Epoch since the Calendar and Member tables cannot change within a given Epoch.</p></li>
 
−
</ul></li>
 
−
<li><p>Making Changes to the Load Balancer Configuration<br />This section assumes that the load balancer is in-service and as such, care must be taken to avoid service disruption during reconfiguration. If the load balancer is out-of-service, you can reconfigure it using the Initialization steps above without care for disruption.</p>
 
−
<p>Any Epoch that is reachable (connected) via the Calendar Epoch Assignment table MUST not be changed. In-service reconfiguration of the load balancer is done by the following steps.</p>
 
−
<ul>
 
−
<li><p>Allocate the next free Calendar Epoch ID: Once we’re done all the rest of the updates, we’ll activate this new Epoch</p></li>
 
−
<li><p>Insert new entries into the Load Balance Member Table for any entries that need to be different in the next Epoch</p></li>
 
−
<li><p>Compute and insert an entirely new calendar into the Load Balance to Member Map Table using the next Calendar Epoch ID</p></li>
 
−
<li><p>Choose an Event ID in the (near) future which will become the boundary between the current Epoch and the new Epoch.</p></li>
 
−
<li><p>Compute a set of Ternary prefix matches over the Event ID space which describe the entire range of Event IDs from the start of the current Epoch up to the start of the new Epoch.</p></li>
 
−
<li><p>Program the ternary prefix matches into the Calendar Epoch Assignment Table</p></li>
 
−
<li><p>Update the wildcard match in the Calendar Epoch Assignment Table to point to the new Epoch</p></li>
 
−
</ul></li>
 
−
<li><p>The new Epoch is activated and MUST NOT be changed</p></li>
 
−
<li><p>After waiting an appropriate time for all events from the previous Epoch to have quiesced, perform the following cleanup steps.</p>
 
−
<ul>
 
−
<li><p>Delete the ternary prefix matches for the previous Epoch from the Calendar Epoch Assignment Table. This disconnects all references for the previous Epoch to the rest of the pipeline tables.</p></li>
 
−
<li><p>Delete the Calendar for the previous Epoch</p></li>
 
−
<li><p>Delete the Member rewrites for the previous Calendar</p></li>
 
−
</ul></li>
 
−
</ul>
 
−
<div class="figure">
 
−
<img src="esnet-JLab-network-diagram-v002d-lb.png" alt="[fig:lb]Load Balancer/Host CPU Processing " /><p class="caption">[fig:lb]Load Balancer/Host CPU Processing </p>
 
−
</div>
 
−
<h1 id="sec:re">Reassembly Engine Processing</h1>
 
−
<p>Time-Stamp aggregated data transferred through network equipment will be fragmented and require reassembly by the RE on behalf of the targeted compute farm destination node. Several candidate designs are being considered as depicted in Figure [fig:reass]:<br /></p>
 
−
<ul>
 
−
<li><p>RE resident () in each compute node in an FPGA accelerated Network Interface Card (NIC) (e.g., Xilinx SN1000)</p></li>
 
−
<li><p>RE resident () in each compute node CPU operating system.</p></li>
 
−
<li><p>RE centralized () in an FPGA residing in a compute farm switch.</p></li>
 
−
</ul>
 
−
<p>Additionally, end compute nodes are individually responsible for informing the LB host CPU of status such that the LB host CPU can make informed decisions in comprising an effective load balancing strategy for the FPGA resident LB.</p>
 
−
<div class="figure">
 
−
<img src="esnet-JLab-network-diagram-v002d-re.png" alt="[fig:reass]Compute Farm Reassembly/Feedback " /><p class="caption">[fig:reass]Compute Farm Reassembly/Feedback </p>
 
−
</div>
 
−
<h1 id="sec:itc">Initial Test Configuration</h1>
 
−
<p>Figure [fig:tst0] depicts a notional EJFAT initial test configuration using commonly available Unix utilities and not initially using a network switch. The sequence of this test configuration is as follows:</p>
 
−
<ul>
 
−
<li><p>Generate a representative ROC PCAP file using the script in section [sec:rocpcap]. This data should emulate a data stream from the DAQ system exhibiting desired sequences in the stream that will test the functionality of the LB.</p></li>
 
−
<li><p>Configure the LB P4 load balancer per the guidelines set forth in section [sec:lbcntrlpln].</p></li>
 
−
<li><p>Use <span><em>tcpreplay</em></span> to send the ROC PCAP file via the test host CPU NIC into the FPGA resident LB via the FPGA’s (bidirectional) QSFP28 optical port.</p></li>
 
−
<li><p>Use <span><em>tcpdump</em></span> to capture the LB response sent back into the test host CPU NIC into an LB PCAP file</p></li>
 
−
<li><p>Use <span><em>Wireshark/tshark</em></span> or other to decode, render, and examine the LB PCAP file to ascertain if the LB provided the correct response. Decoding should be facilitated by using the <span><em>Protocol</em></span> field in the LB meta-data specified in section [sec:Load Balancer Meta-Data] with add-ins for the bit structures defined in sections [sec:Load Balancer Meta-Data], [sec:Reassembly Engine Meta-Data].</p></li>
 
−
<li><p>Use an <span><em>LB config</em></span> process running on the host CPU to setup test conditions with the destination compute farm to alter the LBs routing strategy using the information in sections [sec:cntrl-pln], [sec:lbcntrlpln].</p></li>
 
−
</ul>
 
−
<div class="figure">
 
−
<img src="ejfat-u280_tst0.png" alt="[fig:tst0]EJFAT Test Configuration " /><p class="caption">[fig:tst0]EJFAT Test Configuration </p>
 
−
</div>
 
−
<h2 id="sec:p4cd">LB Data Plane P4 Code</h2>
 
−
<ul>
 
−
<li><p>line 12: These are understood to be MAC addresses</p></li>
 
−
<li><p>line 45: IPV4 options length = (ipv4 <span class="math"> × </span> hdrlen - 5) <span class="math"> × </span> 32</p></li>
 
−
<li><p>line 56: literally “LB” = 0x4c42; c.f. section [sec:Load Balancer Meta-Data] and line 8 section [sec:rocpcap].</p></li>
 
−
<li><p>line 57: LB version; c.f. line 9 section [sec:rocpcap]</p></li>
 
−
<li><p>line 58: protocol; c.f. line 10 section [sec:rocpcap], section [sec:roc]</p></li>
 
−
<li><p>line 150, 301: Gate to ensure in packet is for LB</p></li>
 
−
<li><p>line 174: <span><em>epoch</em></span> is determined by <span><em>largest prefix match</em></span> of <span><em>tick</em></span>; c.f. section [sec:lbcntrlpln] lines 18,25 for epochs 0,1 respectively</p></li>
 
−
<li><p>line 185: lower 9 bits of <span><em>tick</em></span> used for member slot indexing on round-robin basis; all 512 member slots require population for all <span><em>active</em></span> epochs; c.f. line 33 section [sec:lbcntrlpln]</p></li>
 
−
</ul>
 
−
<h2 id="sec:lbcntrlpln">LB Control Plane</h2>
 
−
<p>This is the Vivado P4 simulator control plane configuration script:</p>
 
−
<ul>
 
−
<li><p>lines 1,8: Sets the LB MAC address, IP address for IPV4, IPV6 respectively.</p></li>
 
−
<li><p>line 15: Set up Epoch 0 to match all ticks at low priority (=64)</p></li>
 
−
<li><p>line 22: Set up Epoch 1 to match ticks for which the 2nd least significant nibble=1 and the most significant nibble is arbitrary designating 16 possible tick values for Epoch 1 at higher priority (=5).</p></li>
 
−
<li><p>line 29: Designate member (end-node) 0 for calendar slot 0xa, Epoch 0</p></li>
 
−
<li><p>line 36: Designate member (end-node) 0 for calendar slot 0x14, Epoch 1</p></li>
 
−
<li><p>line 43: Designate member 0 for IPV4 packets as MAC=0x11223344556, IP=0xaabbccdd, Port=0x4556</p></li>
 
−
<li><p>line 52: Designate member 0 for IPV6 packets as MAC=0x11223344556,<br />IP=0xfe8000000000000000000000000000, Port=0x4556</p></li>
 
−
</ul>
 
−
<h2 id="sec:rocpcap">ROC PCAP Generator Script</h2>
 
−
<p>The following Scapy test script can be used to generate the ROC PCAP file shown in Figure [fig:tst0]:</p>
 
−
<h2 id="sec:scpnstl">Scapy Installation</h2>
 
−
<p>Scapy may be installed by executing the following command at the Unix command line:</p>
 
−
<pre><code>    pip3 install --user scapy</code></pre>
 
−
<h2 id="sec:rocpcapmta">ROC PCAP Meta Data File</h2>
 
−
<p>In the following file:</p>
 
−
<p>Each row (1...n) in this file matches with the corresponding packet (1...n) in the packets<span>_</span>in.pcap file. ( Lines 42, 46 in section [sec:rocpcap] )<br /></p>
 
−
<p>The simulator loads a line from this file and uses it to initialize the short<span>_</span>metadata struct which is processed along with the corresponding packet data.<br /></p>
 
−
<p>You should find references to “short<span>_</span>metadata” struct in the p4 program.<br /></p>
 
−
<p>I have no idea what the sim does when it has more packets in the .pcap file than the number of lines in the .meta file. In general, all of these fields may be relevant. For the load balancer specifically, the only field that matters is really the “egress<span>_</span>spec” field. On the way in, it contains the *ingress* port. It isn’t touched by the p4 program since we always want the output packet to go back out the exact same interface that it arrived on (after we rewrite the destination header fields of course).<br /></p>
 
−
<p>The p4bm simulator does something like this:</p>
 
−
<pre><code>   
 
−
open packets_in.pcap for read
 
−
open packets_in.meta for read
 
−
open packets_out.pcap for write
 
−
open packets_out.meta for write
 
−
while (!done) {
 
−
    read packet p from packets_in.pcap
 
−
    read metadata row m from packets_in.meta
 
−
    (out_packet, out_meta) = simulate_the_p4(p, m)
 
−
    write out_packet to packets_out.pcap
 
−
    write out_meta to packets_out.meta</code></pre>
 
−
<p>The pcap-generator.py script isn’t directly used by the p4bm sim. That’s just something I wrote to help you to make up input packets for the simulator so you didn’t have to make your input packets (as seen in packets<span>_</span>in.pcap) by hand.<br /></p>
 
−
<p>There is a 1:1 correspondence between calls to write<span>_</span>packet() in the pcap-generator.py script and packets in the packets<span>_</span>in.pcap file.<br /></p>
 
−
<p>The .py program spits out 2 interleaved ROC transfers (one transfer is carried in IPv4, the other is in IPv6). Each ROC transfer starts out as 1050 bytes of EVIO6 data. It is then segmented into 100 byte segments, ready to be put into a packet. Each segment gets a EVIO6 Segmentation header added to keep track of which segment it is, then each segment gets a UDP Load Balancer header added to give the load-balancer its context.<br /></p>
 
−
<p>Each call to write<span>_</span>packet() spits out one of the segments in either a IPv4 or IPv6 encapsulation.<br /></p>
 
−
<p>The program might be more clear if you were to duplicate the loop (one loop for IPv4 and one loop for IPv6) and put a single call to write<span>_</span>packet() in each of the loops. That might make it more clear that it was 2 transfers since they would no longer be interleaved.<br /></p>
 
−
<p>The 2 lines in packets<span>_</span>in.meta will be used for the first 2 packets in the packets<span>_</span>in.pcap file. As currently written, one of those lines will be for the first segment in IPv4 and the second line will be for the first segment in IPv6. As I mentioned before, I’m actually not certain what happens after that in the simulator. In practice, it shouldn’t be important for this pipeline since it doesn’t get modified by the p4 program at all.</p>
 
−
<h2 id="sec:tsrklb">Tshark Plug-in for LB Meta-Data</h2>
 
−
<p>In the following file:</p>
 
−
<h2 id="sec:tsrke6">Tshark Plug-in for Payload Seg</h2>
 
−
<p>In the following file:</p>
 
−
<p><span>99</span></p>
 
−
<p>Author, A.N and Another, A. N., 2010, MNRAS, 431, 28.</p>
 
−
<h1 id="appendix:ejfat">Appendix: EJFAT Processing</h1>
 
−
<div class="figure">
 
−
<img src="esnet-jlab-network-diagram-v002d.png" alt="[fig:ejfat]EJFAT Load Balanced Transport. " /><p class="caption">[fig:ejfat]EJFAT Load Balanced Transport. </p>
 
−
</div>
 
−
</body>
 
−
</html>
 

Revision as of 17:51, 7 May 2024

Welcome to the EJFAT Wiki

(ESnet / JLaB FPGA Accelerated Transport)


System Overview:

EJFAT is a collaboration between Energy Sciences Network (ESnet) and Thomas Jefferson National Laboratory (JLab) for proof of concept engineering to program a Field Programmable Gate Array (FPGA) for network data routing of commonly tagged UDP packets from any data source to individual and configurable destination endpoints in an end-point compute work load balanced manner, including some additional tagging for stream reassembly at the endpoint. The primary purpose of this FPGA based acceleration is to load balance work to destination compute farm endpoints with low latency and full line rate bandwidth of 100 Gbs with feedback from the destination compute farm.

EJFAT System Status

ejfat-1

  1. 200Gbps NIC: ejfat-1-daq 129.57.177.8
  2. 10Gbps NIC: ejfat-1 129.57.177.131
  3. U280 FPGA: ejfat-1-dp 129.57.177.11
  4. Test moving a current LB install wholesale by moving files/containers
  5. IT Account Setup Sandbox

ejfat-2

  1. 200Gbps NIC: ejfat-2-daq 129.57.177.2
  2. 10Gbps NIC: ejfat-2 129.57.177.132
  3. U280 FPGA: ejfat-2-dp 129.57.177.12
  4. LB: DP latest prod FW, CP Main branch Jan 4 Rev, CP/FW upgrades pending
  5. IOMMU enabled

ejfat-3

  1. 200Gbps NIC: ejfat-3-daq 129.57.177.3
  2. 10Gbps NIC: ejfat-3 129.57.177.133
  3. U280 FPGA: ejfat-3-dp 129.57.177.13
  4. Ready to accept second FPGA - needs addition PCIe riser

ejfat-4

  1. 200Gbps NIC: ejfat-4-daq 129.57.177.4
  2. 10Gbps NIC: ejfat-4 129.57.177.134
  3. U280 FPGA: ejfat-4-dp 129.57.177.14
  4. XDP experiments

ejfat-5

  1. 200Gbps NIC: ejfat-5-daq 129.57.177.5
  2. 10Gbps NIC: ejfat-5 129.57.177.135
  3. U280 FPGA: ejfat-5-dp 129.57.177.15
  4. LB: DP latest prod FW, CP Dev branch April 11 Rev (Latest)

ejfat-6

  1. 200Gbps NIC: ejfat-6-daq 129.57.177.6
  2. 10Gbps NIC: ejfat-6 129.57.177.136
  3. U280 FPGA: ejfat-6-dp 129.57.177.16
  4. DAOS experiments
  5. IOMMU enabled

ejfat-fs

  1. 200Gbps NIC: ejfat-fs-daq 129.57.177.7
  2. 10Gbps NIC: ejfat-fs 129.57.177.130
  3. U280 FPGA: ejfat-fs-dp 129.57.177.10
  4. Hosts NVME memory/disk

Presentations/Papers

date presenter Event links
2021-03-01 G. Heyes EJFAT Proposal Word
2021-10-21 M. S. Goodrich Div Brief PDF
2021-11-05 M. S. Goodrich Canisius College PDF
2021-12-03 S. Sheldon ESnet LB Tutorial MP4
2021-12-10 Y. Kumar SRO iX Presentation PPTX
2022-08-05 M. S. Goodrich RT-2022 Presentation PPTX
2022-08-05 M. S. Goodrich, et al. RT-2022 Proceedings PDF
2022-10-20 S. Sheldon, et al. INDIS-2022 PDF
2022-10-24 M. S. Goodrich ACAT-2022 Presentation PPTX
2023-03-17 M. S. Goodrich, et al. ACAT-2022 Proceedings PDF
2023-05-11 M. S. Goodrich, et al. CHEP-2023 Presentation PPTX
2023-10-12 D. Howard, et al. CHEP-2023 Conference Publication PDF
2024-03-11 M. S. Goodrich, et al. ACAT-2024 Presentation PPTX
2024-04-10 M. S. Goodrich, et al. RT-2024 Presentation PPTX

EJFAT Weekly EPSCI Meetings

EJFAT Weekly EPSCI Meetings

EJFAT Weekly Collaboration Meetings

EJFAT Weekly Meetings

Technical Design Overview

EJFAT Technical Design Overview

UDP Packet Header Formats

IRIAD/EJFAT Testbed

UDP Transmission Performance

EJFAT UDP General Information

EJFAT UDP General Performance Considerations

EJFAT UDP Packet Receiving and Core Switching

EJFAT UDP Packet Sending and NUMA Nodes

EJFAT UDP Single Thread Packet Sending and Receiving

Testing Load Balancer Bandwidth

HOW-TOs

How to setup ejfat nodes

How to install, build and use gRPC

How to install, build and use XDP related packages

How to Compute Schedule Density from PID Signals

EJFAT API

Edge to Core Test Equipment:

  1. Price Estimate Spreadsheet
  2. Networking Diagram, Updated (PDF) (from Brent 2024-02-09)
  3. PR408549 : Requisition 1 of 2 :
    1. Statement of Work for Servers
    2. 1/13/2022: EJFAT team decided to solicit two bid responses, one with MLX NIC and one without. Response from Procurement is "I can ask for the two separate quotes. If you are going to purchase both option (with & without add-in cards), once I receive the quotes back, you will have submit a new PR to cover the option (without add-in cards)."
    3. 1/18/2022: Question from KOI Computers: "please clarify what the part number for the NVIDIA Dual Port ConnectX-6". Replied with part # MCX623106AN-CDAT.
    4. 1/24/2022: Requisition currently open for bid responses from vendors. Due date is COB 1/24/2022.
    5. 1/27/2022: PO awarded to Atipa for 6 servers and 1 file-server with FPGA and MLX SmartNIC. Expected delivery date from vendor is 5/31/2022.
  4. PR408870 PR408938 Requisition 2 of 2: Statement of Work for Switches & Cables
    1. 1/14/2022: PRs for the switches, transceivers and fiber have been submitted. I added (4) 2km 100G transceivers to support dual 100G connections between the switches. We can always upgrade to 400G in the future, if needed.
  5. PR409850 NVIDIA ARM HPC Developer Kit
    1. Hardware Specifications for dev kit
      Model GIGABYTE G242-P32, 2U server
      CPU 1x Ampere Altra Q80-30 (Arm processor)
      Memory 512G DDR4 memory
      Storage 6TB SAS/ SATA 3.5″
      GPU 2x NVIDIA A100 GPU
      Network 2x NVIDIA® BlueField®-2 E-Series DPU, 200GbE/HDR single-port QSFP56, PCIe Gen4 x16, secure boot enabled, crypto disabled, 16GB on-board DDR, 1GbE OOB management

Resources

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